| 2026 | ASPDAC | C3PO: Commercial-Quality Global Placement via Coherent, Concurrent Timing, Routability, and Wirelength Optimization. | Yi-Chen Lu, Hao-Hsiang Hsiao, Rongjian Liang, Wen-Hao Liu, Haoxing Ren |
| 2026 | ASPDAC | Differentiable Tier Assignment for Timing and Congestion-Aware Routing in 3D ICs. | Yuan-Hsiang Lu, Hao-Hsiang Hsiao, Yi-Chen Lu, Haoxing Ren, Sung Kyu Lim |
| 2025 | DAC | InsightAlign: A Transferable Physical Design Recipe Recommender Based on Design Insights. | Hao-Hsiang Hsiao, Sudipto Kundu, Wei Zeng, Wei-Ting Chan, Deyuan Guo, Sung Kyu Lim |
| 2025 | DAC | DCO-3D: Differentiable Congestion Optimization in 3D ICs. | Hao-Hsiang Hsiao, Yi-Chen Lu, Pruek Vanna-Iampikul, Anthony Agnesina, Rongjian Liang, Yuan-Hsiang Lu, Haoxing Ren, Sung Kyu Lim |
| 2025 | ICCAD | BUFFALO: PPA-Configurable, LLM-based Buffer Tree Generation via Group Relative Policy Optimization. | Hao-Hsiang Hsiao, Yi-Chen Lu, Sung Kyu Lim, Haoxing Ren |
| 2025 | ICCAD | Invited Paper: LLM-Enhanced GPU-Optimized Physical Design at Scale. | Yi-Chen Lu, Hao-Hsiang Hsiao, Haoxing Ren |
| 2024 | DAC | ML-based Physical Design Parameter Optimization for 3D ICs: From Parameter Selection to Optimization. | Hao-Hsiang Hsiao, Pruek Vanna-Iampikul, Yi-Chen Lu, Sung Kyu Lim |