| 2017 | ISCAS | Efficient implementation of modular multiplication by constants applied to RNS reverse converters. | Roberto de Matos, Rogerio Paludo, Nikolay I. Chervyakov, Pavel Alekseevich Lyakhov, Hctor Pettenghi |
| 2015 | ISCAS | RNS reverse converters based on the new Chinese Remainder Theorem I. | Hctor Pettenghi, Leonel Sousa |
| 2014 | ISCAS | Method for designing multi-channel RNS architectures to prevent power analysis SCA. | Hctor Pettenghi, Jude Angelo Ambrose, Ricardo Chaves, Leonel Sousa |
| 2013 | ASPDAC | DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks. | Jude Angelo Ambrose, Hctor Pettenghi, Leonel Sousa |
| 2012 | ASPDAC | Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion. | Hctor Pettenghi, Leonel Sousa, Jude Angelo Ambrose |
| 2012 | DSD | RNS Arithmetic Units for Modulo {2^n+-k}. | Pedro Miguens Matutino, Hctor Pettenghi, Ricardo Chaves, Leonel Sousa |
| 2008 | ISCAS | A novel contribution to the RTD-based threshold logic family. | Hctor Pettenghi, Maria J. Avedillo, Jos M. Quintana |
| 2007 | ISCAS | Non Return Mobile Logic Family. | Hctor Pettenghi, Maria J. Avedillo, Jos M. Quintana |
| 2006 | ISCAS | Self-latching operation limits for MOBILE circuits. | Jos M. Quintana, Maria J. Avedillo, Hctor Pettenghi |
| 2004 | IJCNN | RTD-based compact programmable gates. | Jos M. Quintana, Maria J. Avedillo, Hctor Pettenghi |
| 2004 | ISCAS | Programmable logic gate based on resonant tunnelling devices. | Jos M. Quintana, Maria J. Avedillo, Hctor Pettenghi |