He Peng
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
5
Active years
2007–2020
Best venue rank
A
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2020 | IECON | Modulation Coordinated Voltage Balance Strategy for a Single-Phase Nine-Level T-type Converter. | Shaoqiang Hu, Lei Li, He Peng, Cheng Wang |
| 2009 | ASPDAC | Parallel transistor level circuit simulation using domain decomposition methods. | He Peng, Chung-Kuan Cheng |
| 2009 | DATE | Reliability aware through silicon via planning for 3D stacked ICs. | Amirali Shayan Arani, Xiang Hu, He Peng, Chung-Kuan Cheng, Wenjian Yu, Mikhail Popovich, Thomas Toms, Xiaoming Chen |
| 2009 | DATE | Parallel transistor level full-chip circuit simulation. | He Peng, Chung-Kuan Cheng |
| 2008 | DATE | Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. | Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng |
| 2007 | ICCD | Fast power network analysis with multiple clock domains. | Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng |
| 2007 | ISCAS | Fast Transient Simulation of Lossy Transmission Lines. | He Peng, Chung-Kuan Cheng |