| 2025 | DAC | Logic Restructuring with Preserved Logic Blocks. | Siang-Yun Lee, Heinz Riener, Sascha Richter, Ankush Sood |
| 2024 | DAC | Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration. | Siang-Yun Lee, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli |
| 2022 | ASPDAC | A Versatile Mapping Approach for Technology Mapping and Graph Optimization. | Alessandro Tempia Calvino, Heinz Riener, Shubham Rai, Akash Kumar, Giovanni De Micheli |
| 2022 | ASPDAC | Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis. | Heinz Riener, Siang-Yun Lee, Alan Mishchenko, Giovanni De Micheli |
| 2022 | DAC | Beyond local optimality of buffer and splitter insertion for AQFP circuits. | Siang-Yun Lee, Heinz Riener, Giovanni De Micheli |
| 2021 | ASPDAC | Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits. | Eleonora Testa, Siang-Yun Lee, Heinz Riener, Giovanni De Micheli |
| 2021 | DATE | Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies. | Shubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar |
| 2021 | DATE | From Boolean functions to quantum circuits: A scalable quantum compilation flow in C++. | Bruno Schmitt, Fereshte Mozafari, Giulia Meuli, Heinz Riener, Giovanni De Micheli |
| 2021 | DDECS | Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition. | Siang-Yun Lee, Heinz Riener, Giovanni De Micheli |
| 2020 | DATE | Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle. | Victor N. Kravets, Jie-Hong R. Jiang, Heinz Riener |
| 2020 | DATE | Exact DAG-Aware Rewriting. | Heinz Riener, Alan Mishchenko, Mathias Soeken |
| 2020 | DATE | A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks. | Eleonora Testa, Mathias Soeken, Heinz Riener, Luca G. Amar, Giovanni De Micheli |
| 2020 | DSD | Revisiting Explicit Enumeration for Exact Synthesis. | Gianluca Martino, Heinz Riener, Grschwin Fey |
| 2019 | DAC | Scalable Generic Logic Synthesis: One Approach to Rule Them All. | Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amar, Giovanni De Micheli, Mathias Soeken |
| 2019 | DATE | On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis. | Heinz Riener, Winston Haaswijk, Alan Mishchenko, Giovanni De Micheli, Mathias Soeken |
| 2019 | FDL | Exact Synthesis of LTL Properties from Traces. | Heinz Riener |
| 2019 | RC | Evaluating ESOP Optimization Methods in Quantum Compilation Flows. | Giulia Meuli, Bruno Schmitt, Rdiger Ehlers, Heinz Riener, Giovanni De Micheli |
| 2017 | ASPDAC | CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification. | Heinz Riener, Rdiger Ehlers, Grschwin Fey |
| 2016 | FDL | Designing reliable cyber-physical systems overview associated to the special session at FDL'16. | Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Grschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Knighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Rck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao |
| 2016 | FDL | Equivalence checking on ESL utilizing a priori knowledge. | Niels Thole, Heinz Riener, Grschwin Fey |
| 2016 | ICCAD | Exact diagnosis using boolean satisfiability. | Heinz Riener, Grschwin Fey |
| 2015 | DDECS | Equivalence Checking on System Level Using a Priori Knowledge. | Niels Thole, Heinz Riener, Grschwin Fey |
| 2014 | FDL | MetaSMT: a unified interface to SMT-LIB2. | Heinz Riener, Mathias Soeken, Clemens Werther, Grschwin Fey, Rolf Drechsler |
| 2013 | DATE | Improving fault tolerance utilizing hardware-software-co-synthesis. | Heinz Riener, Stefan Frehse, Grschwin Fey |
| 2012 | MEMOCODE | Model-based diagnosis versus error explanation. | Heinz Riener, Grschwin Fey |
| 2011 | ICST | Test Case Generation from Mutants Using Model Checking Techniques. | Heinz Riener, Roderick Bloem, Grschwin Fey |