| 2008 | IRI | Route selection algorithm based on integer operation Ant Colony Optimization. | Masaya Yoshikawa, Hidekazu Terai |
| 2007 | IRI | Architecture for high-speed Ant Colony Optimization. | Masaya Yoshikawa, Hidekazu Terai |
| 2006 | CAINE | Co-evolutionary robotics using two kinds of neural networks. | Masaya Yoshikawa, Hidekazu Terai |
| 2006 | CATA | Immune Algorithm Processor. | Masaya Yoshikawa, Masahiro Fukui, Hidekazu Terai |
| 2006 | SERA | Apriori, Association Rules, Data Mining, Frequent Itemsets Mining (FIM), Parallel Computing. | Masaya Yoshikawa, Hidekazu Terai |
| 2005 | CEC | Performance driven placement technique based on collaboration of software and hardware. | Masaya Yoshikawa, Hidekazu Terai |
| 2005 | ISDA | A Hierarchical Parallel Placement Technique based on Genetic Algorithm. | Masaya Yoshikawa, Hidekazu Terai |
| 2005 | SERA | Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique. | Masaya Yoshikawa, Hidekazu Terai |
| 2004 | ISCAS | VLSI processor architecture for real-time GA processing and PE-VLSI design. | Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi |
| 2002 | ICASSP | Scalable GA processor architecture and its implementation of processor-element. | Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi |
| 1994 | DAC | Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1. | Hidekazu Terai, Kazutoshi Gemma, Yohsuke Nagao, Yasuo Satoh, Yasuhiro Ohno |
| 1991 | DAC | Basic Concepts of Timing-oriented Design Automation for High-performance Mainframe Computers. | Hidekazu Terai, Fumio Goto, Katsuro Wakai, Tokinori Kozawa, Mitsugu Edagawa, Satoshi Hososaka, Masahiro Hashimoto |
| 1988 | DAC | Automatic Layout Procedures for Serial Routing Devices. | Yasushi Ogawa, Hidekazu Terai, Tokinori Kozawa |
| 1986 | DAC | Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs. | Yasushi Ogawa, Tatsuki Ishii, Yoichi Shiraishi, Hidekazu Terai, Tokinori Kozawa, Kyoji Yuyama, Kyoji Chiba |
| 1985 | DAC | A routing procedure for mixed array of custom macros and standard cells. | Hidekazu Terai, Michiyoshi Hayase, Tokinori Kozawa |
| 1984 | DAC | Combine and top down block placement algorithm for hierarchical logic VLSI layout. | Tokinori Kozawa, Chihei Miura, Hidekazu Terai |
| 1983 | DAC | Automatic placement algorithms for high packing density V L S I. | Tokinori Kozawa, Hidekazu Terai, Tatsuki Ishii, Michiyoshi Hayase, Chihei Miura, Yasushi Ogawa, Kuniaki Kishida, Norio Yamada, Yasuhiro Ohno |