Hirofumi Nakano
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2001–2008
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2008 | ISPA | Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API. | Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara |
| 2001 | SMC | Bolt tightening control using neural networks. | Toru Fujinaka, Hirofumi Nakano, Sigeru Omatu |