How-Rern Lin
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
1994–2010
Best venue rank
B
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2010 | ASPDAC | Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. | Tsung-Yi Wu, Tzi-Wei Kao, Shi-Yi Huang, Tai-Lun Li, How-Rern Lin |
| 1995 | ASPDAC | Power recduction by gate sizing with path-oriented slack calculation. | How-Rern Lin, TingTing Hwang |
| 1994 | ICCAD | Dynamical identification of critical paths for iterative gate sizing. | How-Rern Lin, TingTing Hwang |