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Howard M. Heys

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

10

Venues

8

Active years

1994–2022

Best venue rank

A*

Where they publish

Papers

10 indexed papers, newest first.

Year	Venue	Title	Authors
2022	ISCAS	Variation-Aware Analog Circuit Sizing in Carbon Nanotube.	Zahra Heshmatpour, Lihong Zhang, Howard M. Heys
2018	ACISP	Distributed Time-Memory Tradeoff Attacks on Ciphers - (with Application to Stream Ciphers and Counter Mode).	Howard M. Heys
2013	ISCAS	Analytic modeling of interconnect capacitance in submicron and nanometer technologies.	Gholamreza Shomalnasab, Howard M. Heys, Lihong Zhang
2008	DSD	PUFFIN: A Novel Compact Block Cipher Targeted to Embedded Digital Systems.	Huiju Cheng, Howard M. Heys, Cheng Wang
2008	ISCAS	Compact ASIC implementation of the ICEBERG block cipher with concurrent error detection.	Huiju Cheng, Howard M. Heys
2006	AICCSA	Architecture and Performance Analysis of the Multicast Balanced Gamma Switch for Broadband Communications1.	Cheng Li, Ramachandran Venkatesan, Howard M. Heys
2002	ICCCN	Design and implementation of the scalable multicast balanced gamma (BG) switch.	Cheng Li, Howard M. Heys, Ramachandran Venkatesan
2002	ICISC	Hardware Design and Analysisof Block Cipher Components.	Lu Xiao, Howard M. Heys
2001	INFOCOM	An Analysis of the Statistical Self-Synchronization of Stream Ciphers.	Howard M. Heys
1994	CCS	The Design of Substitution-Permutation Networks Resistant to Differential and Linear Cryptanalysis.	Howard M. Heys, Stafford E. Tavares