Hratch Mangassarian
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
10
Venues
4
Active years
2005–2012
Best venue rank
A
Where they publish
Papers
10 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2012 | ASPDAC | On error tolerance and Engineering Change with Partially Programmable Circuits. | Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita |
| 2012 | DATE | Non-solution implications using reverse domination in a modern SAT-based debugging environment. | Bao Le, Hratch Mangassarian, Brian Keng, Andreas G. Veneris |
| 2011 | ICCAD | Debugging with dominance: On-the-fly RTL debug solution implications. | Hratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour |
| 2010 | DATE | Leveraging dominators for preprocessing QBF. | Hratch Mangassarian, Bao Le, Alexandra Goultiaeva, Andreas G. Veneris, Fahiem Bacchus |
| 2008 | ICCAD | A succinct memory model for automated design debugging. | Brian Keng, Hratch Mangassarian, Andreas G. Veneris |
| 2007 | ASPDAC | Trace Compaction using SAT-based Reachability Analysis. | Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian |
| 2007 | DATE | Maximum circuit activity estimation using pseudo-boolean satisfiability. | Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir |
| 2007 | FMCAD | Improved Design Debugging Using Maximum Satisfiability. | Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah |
| 2007 | ICCAD | A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. | Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Marco Benedetti, Duncan Exon Smith |
| 2005 | DATE | On Statistical Timing Analysis with Inter- and Intra-Die Variations. | Hratch Mangassarian, Mohab Anis |