| 2020 | ISPA | A Heuristic Region-based Concurrency Bug Testing Approach. | Kuo-Cheng Chin, Ren-Song Tsay, Hsin-I Wu |
| 2020 | SAC | VIRA: a virtualization assisted deterministic system-level simulations. | Hsin-I Wu, Ren-Song Tsay, Hsu-Hsun Chin |
| 2018 | DATE | A highly efficient full-system virtual prototype based on virtualization-assisted approach. | Hsin-I Wu, Chi-Kang Chen, Tsung-Ying Lu, Ren-Song Tsay |
| 2017 | INFOCOM | LiCompass: Extracting orientation from polarized light. | Yu-Lin Wei, Hsin-I Wu, Han-Chung Wang, Hsin-Mu Tsai, Kate Ching-Ju Lin, Rayana Boubezari, Hoa Le Minh, Zabih Ghassemlooy |
| 2015 | ASPDAC | Automatic timing-coherent transactor generation for mixed-level simulations. | Li-Chun Chen, Hsin-I Wu, Ren-Song Tsay |
| 2015 | Mobisys | RollingLight: Enabling Line-of-Sight Light-to-Camera Communications. | Hui-Yu Lee, Hao-Min Lin, Yu-Lin Wei, Hsin-I Wu, Hsin-Mu Tsai, Kate Ching-Ju Lin |
| 2013 | DATE | A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulations. | Fan-Wei Yu, Bo-Han Zeng, Yu-Hung Huang, Hsin-I Wu, Che-Rung Lee, Ren-Song Tsay |
| 2012 | DAC | A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation. | Yu-Hung Huang, Yi-Shan Lu, Hsin-I Wu, Ren-Song Tsay |