Hsu-Chieh Lee
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
3
Active years
2010–2013
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2013 | ASPDAC | Symmetrical buffered clock-tree synthesis with supply-voltage alignment. | Xin-Wei Shih, Tzu-Hsuan Hsu, Hsu-Chieh Lee, Yao-Wen Chang, Kai-Yuan Chao |
| 2012 | DAC | A chip-package-board co-design methodology. | Hsu-Chieh Lee, Yao-Wen Chang |
| 2012 | DAC | Obstacle-avoiding free-assignment routing for flip-chip designs. | Po-Wei Lee, Hsu-Chieh Lee, Yuan-Kai Ho, Yao-Wen Chang, Chen-Feng Chang, I-Jye Lin, Chin-Fang Shen |
| 2011 | ICCAD | Escape routing for staggered-pin-array PCBs. | Yuan-Kai Ho, Hsu-Chieh Lee, Yao-Wen Chang |
| 2010 | ICCAD | Recent research development in flip-chip routing. | Hsu-Chieh Lee, Yao-Wen Chang, Po-Wei Lee |
| 2010 | ICCAD | High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees. | Xin-Wei Shih, Hsu-Chieh Lee, Kuan-Hsien Ho, Yao-Wen Chang |