Hung Tien Bui
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
1
Active years
2004–2012
Best venue rank
C
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2012 | ISCAS | Pipelined FPGA design of the Goertzel algorithm for exon prediction. | Hung Tien Bui |
| 2011 | ISCAS | Rapid prototyping of the Goertzel algorithm for hardware acceleration of exon prediction. | Michel Voyer, Sylvain-Robert Rivard, Luc Morin, Hung Tien Bui |
| 2010 | ISCAS | Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS). | Marcel Siadjine Njinowa, Hung Tien Bui, Franois R. Boyer |
| 2008 | ISCAS | Design of an all-digital variable length ring oscillator (VLRO) for clock synthesis. | Hung Tien Bui |
| 2007 | ISCAS | A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs. | Bill Pontikakis, Hung Tien Bui, Franois R. Boyer, Yvon Savaria |
| 2004 | ISCAS | Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector. | Hung Tien Bui, Yvon Savaria |