Hwang-Cherng Chow
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
1
Active years
1999–2005
Best venue rank
C
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | ISCAS | A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications. | Hwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, Wu-Shiung Feng |
| 2004 | ISCAS | High performance sense amplifier circuit for low power SRAM applications. | Hwang-Cherng Chow, Shu-Hsien Chang |
| 2003 | ISCAS | A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder. | Hwang-Cherng Chow, I-Chyn Wey |
| 2002 | ISCAS | New pixel-shared design and split-path readout of CMOS image sensor circuits. | Hwang-Cherng Chow, Yung-Kuo Ho |
| 2002 | ISCAS | A 3.3 V 1 GHz high speed pipelined Booth multiplier. | Hwang-Cherng Chow, I-Chyn Wey |
| 1999 | ISCAS | Bidirectional buffer for mixed voltage applications. | Hwang-Cherng Chow |