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Hyunsu Chae

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

6

Venues

4

Active years

2018–2025

Best venue rank

A*

Where they publish

Papers

6 indexed papers, newest first.

YearVenueTitleAuthors
2025ASPDACML-Assisted RF IC Design Enablement: the New Frontier of AI for EDA.Hyunsu Chae, Song Hang Chai, Taiyun Chi, Sensen Li, David Z. Pan
2025ICCADInvited Paper: Towards Generative AI for Analog and RF IC Design: From Spec to Layout.Hyunsu Chae, Seunggeun Kim, Souradip Poddar, Xiaohan Gao, Sensen Li, David Z. Pan
2024ASPDACISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning.Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Zixuan Jiang, Daniel De Araujo, Douglas Wallace, Douglas Winterberg, Adam R. Klivans, David Z. Pan
2024ICCADPulseRF: Physics Augmented ML Modeling and Synthesis for High-Frequency RFIC Design.Hyunsu Chae, Hao Yu, Sensen Li, David Z. Pan
2023DATEISOP: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design.Hyunsu Chae, Bhyrav Mutnury, Keren Zhu, Douglas Wallace, Douglas Winterberg, Daniel De Araujo, Jay Reddy, Adam R. Klivans, David Z. Pan
2018DACTest cost reduction forHyunsu Chae, Joon-Sung Yang