| 2026 | ASPDAC | DCPPC: Digital Computation in Programmable Photonic Circuits. | Jun-Wei Liang, Iris Hui-Ru Jiang, Kai-Hsiang Chiu |
| 2025 | DAC | Harrow: Synthesis of Optical Logic Circuits via Harmonic Mean and Integer Partition. | Jun-Wei Liang, Iris Hui-Ru Jiang, Kai-Hsiang Chiu |
| 2025 | DAC | Generative Model Based Standard Cell Timing Library Characterization. | Hao-Yu Wu, Hsin-Tzu Chang, Shiuan-Yun Ding, Iris Hui-Ru Jiang, Benson Tsao, Vinson Wu, Wei-Kai Shih |
| 2025 | RTCSA | Passing-Order Decision for Three-to-Two Lane Merging of Connected and Autonomous Vehicles. | Cheng-Pei Chien, Ben-Hau Chia, Ching-Yun Chang, Shang-Chien Lin, Iris Hui-Ru Jiang, Changliu Liu, Chung-Wei Lin |
| 2024 | ICCAD | Modern Fixed-Outline Floorplanning with Rectilinear Soft Modules. | Yu-Yang Chen, Yi-Chen Lin, Tzu-Han Hsu, Iris Hui-Ru Jiang, Tung-Chieh Chen, Tai-Chen Chen, Hua-Yu Chang |
| 2023 | DAC | Lightning Talk: All Routes to Timing Closure. | Iris Hui-Ru Jiang |
| 2022 | DAC | Timing macro modeling with graph neural networks. | Kevin Kai-Chun Chang, Chun-Yao Chiang, Pei-Yu Lee, Iris Hui-Ru Jiang |
| 2022 | DATE | Many-Layer Hotspot Detection by Layer-Attentioned Visual Question Answering. | Yen-Shuo Chen, Iris Hui-Ru Jiang |
| 2022 | DATE | Deadlock Analysis and Prevention for Intersection Management Based on Colored Timed Petri Nets. | Tsung-Lin Tsou, Chung-Wei Lin, Iris Hui-Ru Jiang |
| 2022 | ICCAD | Sub-Resolution Assist Feature Generation with Reinforcement Learning and Transfer Learning. | Guan-Ting Liu, Wei-Chen Tai, Yi-Ting Lin, Iris Hui-Ru Jiang, James P. Shiely, Pu-Jen Cheng |
| 2021 | DAC | Subresolution Assist Feature Insertion by Variational Adversarial Active Learning and Clustering with Data Point Retrieval. | Sean Shang-En Tseng, Iris Hui-Ru Jiang, James P. Shiely |
| 2021 | ICCAD | DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper. | Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Seungwon Kim, Victor N. Kravets, Yih-Lang Li, Ravi Varadarajan, Mingyu Woo |
| 2021 | VTC | Efficient Mandatory Lane Changing of Connected and Autonomous Vehicles. | Shang-Chien Lin, Chia-Chu Kung, Lee Lin, Chung-Wei Lin, Iris Hui-Ru Jiang |
| 2020 | ASPDAC | Equivalent Capacitance Guided Dummy Fill Insertion for Timing and Manufacturability. | Sheng-Jung Yu, Chen-Chien Kao, Chia-Han Huang, Iris Hui-Ru Jiang |
| 2020 | DAC | Fast and Accurate Wire Timing Estimation on Tree and Non-Tree Net Structures. | Hsien-Han Cheng, Iris Hui-Ru Jiang, Oscar Ou |
| 2020 | DAC | Routing Topology and Time-Division Multiplexing Co-Optimization for Multi-FPGA Systems. | Tung-Wei Lin, Wei-Chen Tai, Yu-Cheng Lin, Iris Hui-Ru Jiang |
| 2020 | DAC | Late Breaking Results: Design Dependent Mega Cell Methodology for Area and Power Optimization. | Chien-Pang Lu, Iris Hui-Ru Jiang, Chih-Wen Yang |
| 2020 | ICCAD | DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design. | Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo |
| 2020 | ICCAD | Dynamic IR-Drop ECO Optimization by Cell Movement with Current Waveform Staggering and Machine Learning Guidance. | Xuan-Xue Huang, Hsien-Chia Chen, Sheng-Wei Wang, Iris Hui-Ru Jiang, Yih-Chih Chou, Cheng-Hong Tsai |
| 2020 | ICCAD | Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration. | Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen |
| 2019 | DAC | Novel Guiding Template and Mask Assignment for DSA-MP Hybrid Lithography Using Multiple BCP Materials. | Yi-Ting Lin, Iris Hui-Ru Jiang |
| 2019 | ICCAD | DATC RDF-2019: Towards a Complete Academic Reference Design Flow. | Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo |
| 2018 | ASPDAC | FastPass: Fast timing path search for generalized timing exception handling. | Pei-Yu Lee, Iris Hui-Ru Jiang, Tung-Chieh Chen |
| 2018 | DAC | COSAT: congestion, obstacle, and slew aware tree construction for multiple power domain design. | Chien-Pang Lu, Iris Hui-Ru Jiang |
| 2018 | ICCAD | DATC RDF: an academic flow from logic synthesis to detailed routing. | Jinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, Gi-Joon Nam |
| 2017 | DAC | iClaire: A Fast and General Layout Pattern Classification Algorithm. | Wei-Chun Chang, Iris Hui-Ru Jiang, Yen-Ting Yu, Wei-Fang Liu |
| 2017 | DAC | Power and Area Efficient Hold Time Fixing by Free Metal Segment Allocation. | Wei-Lun Chiu, Iris Hui-Ru Jiang, Chien-Pang Lu, Yu-Tung Chang |
| 2017 | DATE | Fast low power rule checking for multiple power domain design. | Chien-Pang Lu, Iris Hui-Ru Jiang |
| 2017 | ICCAD | DATC RDF: Robust design flow database: Invited paper. | Jinwook Jung, Pei-Yu Lee, Yan-Shiun Wu, Nima Karimpour Darav, Iris Hui-Ru Jiang, Victor N. Kravets, Laleh Behjat, Yih-Lang Li, Gi-Joon Nam |
| 2016 | ASPDAC | Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits. | Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang, Bing Li |
| 2016 | DAC | Multiple patterning layout decomposition considering complex coloring rules. | Hua-Yu Chang, Iris Hui-Ru Jiang |
| 2016 | DATE | Resource-aware functional ECO patch generation. | An-Che Cheng, Iris Hui-Ru Jiang, Jing-Yang Jou |
| 2016 | ICCAD | OpenDesign flow database: the infrastructure for VLSI design and design automation research. | Jinwook Jung, Iris Hui-Ru Jiang, Gi-Joon Nam, Victor N. Kravets, Laleh Behjat, Yih-Lang Li |
| 2016 | ICCAD | OWARU: free space-aware timing-driven incremental placement. | Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, Youngsoo Shin |
| 2015 | DAC | Criticality-dependency-aware timing characterization and analysis. | Yu-Ming Yang, King Ho Tam, Iris Hui-Ru Jiang |
| 2015 | ICCAD | iTimerC 2.0: Fast Incremental Timing and CPPR Analysis. | Pei-Yu Lee, Iris Hui-Ru Jiang, Cheng-Ruei Li, Wei-Lun Chiu, Yu-Ming Yang |
| 2015 | ICCAD | GasStation: Power and Area Efficient Buffering for Multiple Power Domain Design. | Chien-Pang Lu, Iris Hui-Ru Jiang, Chin-Hsiung Hsu |
| 2014 | DAC | Functional ECO Using Metal-Configurable Gate-Array Spare Cells. | Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang |
| 2014 | ICCAD | Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations. | Iris Hui-Ru Jiang, Gi-Joon Nam, Hua-Yu Chang, Sani R. Nassif, Jerry Hayes |
| 2014 | ICCAD | The overview of 2014 CAD contest at ICCAD. | Iris Hui-Ru Jiang, Natarajan Viswanathan, Tai-Chen Chen, Jin-Fu Li |
| 2014 | ICCAD | iTimerC: common path pessimism removal using effective reduction methods. | Yu-Ming Yang, Yu-Wei Chang, Iris Hui-Ru Jiang |
| 2014 | ICCAD | DRC-based hotspot detection considering edge tolerance and incomplete specification. | Yen-Ting Yu, Iris Hui-Ru Jiang, Yumin Zhang, Charles C. Chiang |
| 2013 | DAC | Machine-learning-based hotspot detection using topological classification and critical feature extraction. | Yen-Ting Yu, Geng-He Lin, Iris Hui-Ru Jiang, Charles C. Chiang |
| 2013 | ICCAD | The overview of 2013 CAD contest at ICCAD. | Iris Hui-Ru Jiang, Zhuo Li, Hwei-Tseng Wang, Natarajan Viswanathan |
| 2012 | DAC | Timing ECO optimization using metal-configurable gate-array spare cells. | Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang |
| 2012 | DAC | Accurate process-hotspot detection using critical design rule extraction. | Yen-Ting Yu, Ya-Chung Chan, Subarna Sinha, Iris Hui-Ru Jiang, Charles C. Chiang |
| 2012 | ICCAD | Opening: Introduction to CAD contest at ICCAD 2012: CAD contest. | Iris Hui-Ru Jiang, Zhuo Li, Yih-Lang Li |
| 2011 | DAC | Simultaneous functional and timing ECO. | Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang |
| 2011 | ICCAD | Timing ECO optimization via Bzier curve smoothing and fixability identification. | Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang |
| 2010 | ISCAS | Live Demo: ECOS 1.0: A metal-only ECO synthesizer. | Iris Hui-Ru Jiang, Hua-Yu Chang |
| 2009 | DAC | Matching-based minimum-cost spare cell selection for design changes. | Iris Hui-Ru Jiang, Hua-Yu Chang, Liang-Gi Chang, Huang-Bi Hung |
| 2009 | ISCAS | POSA: Power-state-aware Buffered Tree Construction. | Iris Hui-Ru Jiang, Ming-Hua Wu |
| 2008 | ICCD | Power-state-aware buffered tree construction. | Iris Hui-Ru Jiang, Ming-Hua Wu |
| 2008 | ICCD | Configurable rectilinear Steiner tree construction for SoC and nano technologies. | Iris Hui-Ru Jiang, Yen-Ting Yu |
| 2003 | ASPDAC | Simultaneous floorplanning and buffer block planning. | Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao |
| 1999 | ASPDAC | Hierarchical Floorplan Design on the Internet. | Jiann-Horng Lin, Jing-Yang Jou, Iris Hui-Ru Jiang |
| 1999 | DAC | Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. | Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang |
| 1999 | ICCAD | A clustering- and probability-based approach for time-multiplexed FPGA partitioning. | Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang |
| 1999 | ICCAD | Optimum loading dispersion for high-speed tree-type decision circuitry. | Jie-Hong Roland Jiang, Iris Hui-Ru Jiang |