| 2014 | CASES | AdaPNet: Adapting process networks in response to resource variations. | Lars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele |
| 2014 | DAC | Static Mapping of Mixed-Critical Applications for Fault-Tolerant MPSoCs. | Shin-Haeng Kang, Hoeseok Yang, Sungchan Kim, Iuliana Bacivarov, Soonhoi Ha, Lothar Thiele |
| 2014 | DATE | Reliability-aware mapping optimization of multi-core systems with mixed-criticality. | Shin-Haeng Kang, Hoeseok Yang, Sungchan Kim, Iuliana Bacivarov, Soonhoi Ha, Lothar Thiele |
| 2014 | DATE | COOLIP: Simple yet effective job allocation for distributed thermally-throttled processors. | Pratyush Kumar, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele |
| 2014 | ISPA | EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems. | Lars Schor, Iuliana Bacivarov, Luis Gabriel Murillo, Pier Stanislao Paolucci, Frdric Rousseau, Ashraf El Antably, Robert Buecs, Nicolas Fournel, Rainer Leupers, Devendra Rai, Lothar Thiele, Laura Tosoratto, Piero Vicini, Jan Weinstock |
| 2013 | CASES | Expandable process networks to efficiently specify and explore task, data, and pipeline parallelism. | Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele |
| 2013 | EuroPar | Designing Applications with Predictable Runtime Characteristics for the Baremetal Intel SCC. | Devendra Rai, Lars Schor, Nikolay Stoimenov, Iuliana Bacivarov, Lothar Thiele |
| 2013 | EuroPar | Reliable and Efficient Execution of Multiple Streaming Applications on Intel's SCC Processor. | Lars Schor, Devendra Rai, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele |
| 2012 | CASES | Power agnostic technique for efficient temperature estimation of multicore embedded systems. | Devendra Rai, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele |
| 2012 | CASES | Scenario-based design flow for mapping streaming applications onto on-chip many-core systems. | Lars Schor, Iuliana Bacivarov, Devendra Rai, Hoeseok Yang, Shin-Haeng Kang, Lothar Thiele |
| 2012 | DSD | MAMOT: Memory-Aware Mapping Optimization Tool for MPSoC. | Olivera Jovanovic, Peter Marwedel, Iuliana Bacivarov, Lothar Thiele |
| 2012 | RTAS | Worst-Case Temperature Guarantees for Real-Time Applications on Multi-core Systems. | Lars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele |
| 2011 | DAC | Thermal-aware system analysis and software synthesis for embedded multi-processors. | Lothar Thiele, Lars Schor, Hoeseok Yang, Iuliana Bacivarov |
| 2011 | DATE | Worst-case temperature analysis for real-time systems. | Devendra Rai, Hoeseok Yang, Iuliana Bacivarov, Jian-Jia Chen, Lothar Thiele |
| 2006 | DATE | Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application. | Florin Dumitrascu, Iuliana Bacivarov, Lorenzo Pieralisi, Marius Bonaciu, Ahmed Amine Jerraya |
| 2005 | ASPDAC | Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration. | Aimen Bouchhima, Iuliana Bacivarov, Wassim Youssef, Marius Bonaciu, Ahmed Amine Jerraya |
| 2003 | DATE | Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer. | Sungjoo Yoo, Iuliana Bacivarov, Aimen Bouchhima, Yanick Paviot, Ahmed Amine Jerraya |