Jae-Woo Ahn
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2001–2012
Best venue rank
A*
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2012 | ASPLOS | Reducing off-chip memory traffic by selective cache management scheme in GPGPUs. | Hyojin Choi, Jae-Woo Ahn, Wonyong Sung |
| 2012 | ISCAS | Performance analysis of multi-bank DRAM with increased clock frequency. | Su-Jin Cho, Jae-Woo Ahn, Hyojin Choi, Wonyong Sung |
| 2012 | ISCAS | A simulation-based study for DRAM power reduction strategies in GPGPUs. | Hyojin Choi, Kyuyeon Hwang, Jae-Woo Ahn, Wonyong Sung |
| 2010 | ICIP | Parallel implementation of an error diffusion halftoning algorithm with a general purpose graphics processing unit. | Becksang Seong, Jae-Woo Ahn, Wonyong Sung |
| 2001 | ISCAS | Feedback-directed memory disambiguation for embedded multimedia VLIW computing. | Jae-Woo Ahn, Soo-Mook Moon, Wonyong Sung |