| 2025 | DATE | Effective Macro Placement for Very Large Scale Designs Using MCTS Guided by Pre-Trained RL. | Jai-Ming Lin, Zong-Ze Lee, Nan-Chu Lin |
| 2025 | ICCAD | Efficient Analytical Placement Algorithm with Hybrid Fence Region Constraints Using Non-Newtonian Fluid Model. | Jai-Ming Lin, Hung-Wei Hsu, Tan Huang, Chen-Fa Tsai, De-Shiun Fu, Shih-Cheng Huang |
| 2024 | ICCAD | An Effective Analytical Placement Approach to Handle Fence Region Constraint. | Jai-Ming Lin, Wei-Yuan Lin, Yung-Chen Chen, Pin-Yu Chen, Chen-Fa Tsai, De-Shiun Fu, Che-Li Lin |
| 2023 | ICCAD | HyPlace-3D: A Hybrid Placement Approach for 3D ICs Using Space Transformation Technique. | Jai-Ming Lin, Yu-Chien Lin, Hsuan Kung, Wei-Yuan Lin |
| 2023 | ICCAD | Routability-Driven Orientation-Aware Analytical Placement for System in Package. | Jai-Ming Lin, Tsung-Chun Tsai, Rui-Ting Shen |
| 2022 | ICCAD | Routability-Driven Analytical Placement with Precise Penalty Models for Large-Scale 3D ICs. | Jai-Ming Lin, Hao-Yuan Hsieh, Hsuan Kung, Hao-Jia Lin |
| 2022 | ICCAD | A Novel Blockage-Avoiding Macro Placement Approach for 3D ICs Based on POCS. | Jai-Ming Lin, Po-Chen Lu, Heng-Yu Lin, Jia-Ting Tsai |
| 2021 | ICCAD | DAPA: A Dataflow-Aware Analytical Placement Algorithm for Modern Mixed-Size Circuit Designs. | Jai-Ming Lin, Wei-Fan Huang, Yao-Chieh Chen, Yi-Ting Wang, Po-Wen Wang |
| 2021 | ICCAD | Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs. | Jai-Ming Lin, Chung-Wei Huang, Liang-Chi Zane, Min-Chia Tsai, Che-Li Lin, Chen-Fa Tsai |
| 2019 | DAC | Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between Macros. | Jai-Ming Lin, Szu-Ting Li, Yi-Ting Wang |
| 2019 | ICCAD | A Novel Macro Placement Approach based on Simulated Evolution Algorithm. | Jai-Ming Lin, You-Lun Deng, Ya-Chu Yang, Jia-Jian Chen, Yao-Chieh Chen |
| 2018 | DATE | General floorplanning methodology for 3D ICs with an arbitrary bonding style. | Jai-Ming Lin, Chien-Yu Huang |
| 2018 | DATE | Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs. | Jai-Ming Lin, Chien-Yu Huang, Jhih-Ying Yang |
| 2018 | ICCAD | A fast thermal-aware fixed-outline floorplanning methodology based on analytical models. | Jai-Ming Lin, Tai-Ting Chen, Yen-Fu Chang, Wei-Yi Chang, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu |
| 2018 | ICCAD | Macro-aware row-style power delivery network design for better routability. | Jai-Ming Lin, Jhih-Sheng Syu, I-Ru Chen |
| 2017 | ASPDAC | Regularity-aware routability-driven placement prototyping algorithm for hierarchical mixed-size circuits. | Jai-Ming Lin, Bo-Heng Yu, Li-Yen Chang |
| 2016 | ASPDAC | A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. | Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin |
| 2016 | ICCAD | SAINT: handling module folding and alignment in fixed-outline floorplans for 3D ICs. | Jai-Ming Lin, Po-Yang Chiu, Yen-Fu Chang |
| 2012 | ASPDAC | Voltage island-driven floorplanning considering level shifter placement. | Jai-Ming Lin, Wei-Yi Cheng, Chung-Lin Lee, Richard C. Hsu |
| 2012 | ICCAD | Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits. | Cheng-Wu Lin, Chung-Lin Lee, Jai-Ming Lin, Soon-Jyh Chang |
| 2011 | ASPDAC | Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree construction. | Jia-Ru Chuang, Jai-Ming Lin |
| 2011 | DAC | Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits. | Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang |
| 2010 | ASPDAC | UFO: unified convex optimization algorithms for fixed-outline floorplanning. | Jai-Ming Lin, Hsi Hung |
| 2010 | DAC | Performance-driven analog placement considering boundary constraint. | Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang |
| 2005 | ASPDAC | Placement with symmetry constraints for analog layout design using TCG-S. | Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang |
| 2003 | ASPDAC | Graph matching-based algorithms for array-based FPGA segmentation design and routing. | Jai-Ming Lin, Song-Ra Pan, Yao-Wen Chang |
| 2002 | DAC | TCG-S: orthogonal coupling of P | Jai-Ming Lin, Yao-Wen Chang |
| 2002 | DATE | Arbitrary Convex and Concave Rectilinear Module Packing Using TCG. | Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang |
| 2001 | DAC | TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans. | Jai-Ming Lin, Yao-Wen Chang |
| 2001 | ICCD | An Algorithm for Dynamically Reconfigurable FPGA Placement. | Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang |
| 2001 | ICCD | Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning. | Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang |
| 1998 | ICCAD | Graph matching-based algorithms for FPGA segmentation design. | Yao-Wen Chang, Jai-Ming Lin, D. F. Wong |