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Jan Craninckx

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

11

Venues

4

Active years

2003–2021

Best venue rank

A*

Where they publish

Papers

11 indexed papers, newest first.

YearVenueTitleAuthors
2021ISCASFractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation.Pratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx
2012DATEDesign of an intrinsically-linear double-VCO-based ADC with 2Peng Gao, Xinpeng Xing, Jan Craninckx, Georges G. E. Gielen
2010DATEA compact digital amplitude modulator in 90nm CMOS.Vincenzo Chironi, Bjrn Debaillie, Andrea Baschirotto, Jan Craninckx, Mark Ingels
2010DATEAn 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation.Arnd Geis, Pierluigi Nuzzo, Julien Ryckaert, Yves Rolain, Gerd Vandersteen, Jan Craninckx
2010ISCASAn area efficient digital amplitude modulator in 90nm CMOS.Vincenzo Chironi, Bjrn Debaillie, Andrea Baschirotto, Jan Craninckx, Mark Ingels
2009DATEA design methodology for fully reconfigurable Delta-Sigma data converters.Yi Ke, Jan Craninckx, Georges G. E. Gielen
2009ISCASAnalysis of Fractional Spur Reduction using SigmaDelta-noise Cancellation in Digital-PLL.Kameswaran Vengattaramane, Jan Craninckx, Michiel Steyaert
2008GLOBECOMCalibration of SDR Circuit Imperfections.Bjrn Debaillie, Peter Van Wesemael, Jan Craninckx
2006DATEA synthesis tool for power-efficient base-band filter design.Vito Giannini, Pierluigi Nuzzo, Fernando De Bernardinis, Jan Craninckx, Boris Come, Stefano D'Amico, Andrea Baschirotto
2006ISCASFully reconfigurable active-Gm-RC biquadratic cells for software defined radio applications.Vito Giannini, Jan Craninckx, J. Compiet, Boris Come, Stefano D'Amico, Andrea Baschirotto
2003DAC4G terminals: how are we going to design them?Jan Craninckx, Stphane Donnay