| 2015 | DDECS | Mapping Trained Neural Networks to FPNNs. | Martin Krcma, Jan Kastil, Zdenek Kotsek |
| 2014 | DSD | Automatic Construction of On-line Checking Circuits Based on Finite Automata. | Lucie Matuova, Jan Kastil, Zdenek Kotsek |
| 2013 | DDECS | Hardware architecture for the fast pattern matching. | Jan Kastil, Vlastimil Kosar, Jan Korenek |
| 2013 | DDECS | Fault tolerant CAN bus control system implemented into FPGA. | Karel Szurman, Jan Kastil, Martin Straka, Zdenek Kotsek |
| 2012 | DDECS | Test platform for fault tolerant systems design properties verification. | Martin Straka, Lukas Miculka, Jan Kastil, Zdenek Kotsek |
| 2012 | DSD | Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA. | Jan Kastil, Martin Straka, Lukas Miculka, Zdenek Kotsek |
| 2011 | DDECS | Advanced fault tolerant bus for multicore system implemented in FPGA. | Martin Straka, Jan Kastil, Jaroslav Novotn, Zdenek Kotsek |
| 2011 | DSD | SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems. | Martin Straka, Jan Kastil, Zdenek Kotsek |
| 2010 | DDECS | Hardware accelerated pattern matching based on Deterministic Finite Automata with perfect hashing. | Jan Kastil, Jan Korenek |
| 2010 | DDECS | Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs. | Martin Straka, Jan Kastil, Zdenek Kotsek |
| 2010 | DSD | Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration. | Martin Straka, Jan Kastil, Zdenek Kotsek |
| 2009 | DSD | Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing. | Jan Kastil, Jan Korenek, Ondrej Lengl |