Jean Jyh-Jiun Shann
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
5
Active years
1998–2015
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2015 | UIC | Instruction Emulation and OS Supports of a Hybrid Binary Translator for x86 Instruction Set Architecture. | I-Chun Liu, I-Wei Wu, Jean Jyh-Jiun Shann |
| 2008 | DAC | ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor. | Po-Chun Chang, I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung |
| 2008 | DATE | Instruction Set Extension Exploration in Multiple-Issue Architecture. | I-Wei Wu, Zhiyuan Chen, Jean Jyh-Jiun Shann, Chung-Ping Chung |
| 2006 | CCS | Design and implementation of a reconfigurable hardware for secure embedded systems. | Kuen-Cheng Chiang, Zhi-Wei Chen, Jean Jyh-Jiun Shann |
| 1998 | ICPADS | Decoding Unit with High Issue Rate for X86 Superscalar Microprocessors. | S.-K. Cheng, R.-Ming Shiu, Jean Jyh-Jiun Shann |
| 1998 | ICPADS | An X86 Load/Store Unit with Aggressive Scheduling of Load/Store Operations. | Hui-Yue Hwang, R.-Ming Shiu, Jean Jyh-Jiun Shann |