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Jean-Michel Sallese

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

3

Venues

2

Active years

2006–2015

Best venue rank

C

Where they publish

Papers

3 indexed papers, newest first.

YearVenueTitleAuthors
2015ISCASSubstrate noise modeling with dedicated CAD framework for smart power ICs.Hao Zou, Yasser Moursy, Ramy Iskander, Camillo Stefanucci, Pietro Buccella, Maher Kayal, Jean-Michel Sallese
2011ISCASMeshing strategy of equivalent substrate schematic in SMART power IC.Fabrizio Lo Conte, Jean-Michel Sallese, Maher Kayal
2006FDLCompact Modeling of Emerging Technologies with VHDL-AMS.Fabien Prgaldiny, Christophe Lallement, B. Diagne, Jean-Michel Sallese, Franois Krummenacher