| 2010 | DAC | New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture model. | Jer-Min Jou, Sih-Sian Wu, Yun-Lung Lee, Cheng Chou, Yuan-Long Jeang |
| 2009 | AICCSA | A high-speed and decentralized arbiter design for NoC. | Yun-Lung Lee, Jer-Min Jou, Yen-Yu Chen |
| 2001 | ISCAS | Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme. | Jer-Min Jou, Yeu-Horng Shiau, Chin-Chi Liu |
| 1999 | ASPDAC | Hazard-Free Synthesis and Decomposition of Asynchronous Circuits. | Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau |
| 1999 | ASPDAC | A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform. | Jer-Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Ming-Shiang Liang |
| 1999 | ASPDAC | A New Pipelined Architecture for Fuzzy Color Correction. | Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau |
| 1995 | ISCAS | Distributed Diagnostic Fault Simulation for Synchronous Sequential Circuits by Dynamic Fault Partitioning. | Jer-Min Jou, Shung-Chih Chen |
| 1994 | ICCAD | A fast and memory-efficient diagnostic fault simulation for sequential circuits. | Jer-Min Jou, Shung-Chih Chen |
| 1994 | ISCAS | A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial Circuits. | Jer-Min Jou, Shung-Chih Chen, Ren-Der Chen |
| 1994 | ISCAS | Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization. | Jer-Min Jou, Ren-Der Chen, Shiann-Rong Kuang |
| 1993 | ICCD | Library-Adaptively Integrated Data Path Synthesis for DSP Systems. | Jer-Min Jou, Shiann-Rong Kuang |