| 2007 | DAC | Memory Modeling in ESL-RTL Equivalence Checking. | Alfred Klbl, Jerry R. Burch, Carl Pixley |
| 2005 | ASPDAC | Detecting support-reducing bound sets using two-cofactor symmetries. | Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch |
| 2004 | EMSOFT | Conservative approximations for heterogeneous design. | Roberto Passerone, Jerry R. Burch, Alberto L. Sangiovanni-Vincentelli |
| 2001 | EMSOFT | Using Multiple Levels of Abstractions in Embedded Software Design. | Jerry R. Burch, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli |
| 1998 | ICCAD | Robust latch mapping for combinational equivalence checking. | Jerry R. Burch, Vigyan Singhal |
| 1998 | ICCAD | Tight integration of combinational verification methods. | Jerry R. Burch, Vigyan Singhal |
| 1997 | DAC | Safe BDD Minimization Using Don't Cares. | Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan |
| 1996 | DAC | Techniques for Verifying Superscalar Microprocessors. | Jerry R. Burch |
| 1996 | FMCAD | Mechanically Checking a Lemma Used in an Automatic Verification Tool. | Phillip J. Windley, Jerry R. Burch |
| 1995 | ICCAD | Efficient validity checking for processor verification. | Robert B. Jones, David L. Dill, Jerry R. Burch |
| 1994 | CAV | Automatic verification of Pipelined Microprocessor Control. | Jerry R. Burch, David L. Dill |
| 1993 | ICCAD | Efficient verification of determinate speed-independent circuits. | Peter A. Beerel, Jerry R. Burch, Teresa H.-Y. Meng |
| 1993 | ICCAD | Modeling hierarchical combinational circuits. | Jerry R. Burch, David L. Dill, Elizabeth Wolf, Giovanni De Micheli |
| 1992 | ICCAD | Efficient Boolean function matching. | Jerry R. Burch, David E. Long |
| 1992 | ICCD | Delay Models for Verifying Speed-Dependent Asynchronous Circuits. | Jerry R. Burch |
| 1991 | DAC | Using BDDs to Verify Multipliers. | Jerry R. Burch |
| 1991 | DAC | Representing Circuits More Efficiently in Symbolic Model Checking. | Jerry R. Burch, Edmund M. Clarke, David E. Long |
| 1990 | CAV | Verifying Liveness Properties by Verifying Safety Properties. | Jerry R. Burch |
| 1990 | DAC | Sequential Circuit Verification Using Symbolic Model Checking. | Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill |
| 1990 | LICS | Symbolic Model Checking: 10^20 States and Beyond | Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill, L. J. Hwang |
| 1989 | ICCD | Modeling timing assumptions with trace theory. | Jerry R. Burch |