| 2008 | ASPDAC | Experiences of low power design implementation and verification. | Shi-Hao Chen, Jiing-Yuan Lin |
| 2007 | ASPDAC | DFM/DFY practices during physical designs for timing, signal integrity, and power. | Shi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-Hong Tsai |
| 2005 | DATE | Integration, Verification and Layout of a Complex Multimedia SOC. | Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin |
| 2000 | ASPDAC | A new method for constructing IP level power model based on power sensitivity. | Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou |
| 1997 | ASPDAC | CB-Power: a hierarchical cell-based power characterization and estimation environment for static CMOS circuits. | Wen-Zen Shen, Jiing-Yuan Lin, Jyh-Ming Lu |
| 1997 | ICCAD | A power modeling and characterization method for macrocells using structure information. | Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou |
| 1996 | ICCAD | A power modeling and characterization method for the CMOS standard cell library. | Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou |
| 1995 | ASPDAC | Transistor reordering rules for power reduction in CMOS gates. | Wen-Zen Shen, Jiing-Yuan Lin, Fong-Wen Wang |
| 1994 | ICCAD | A cell-based power estimation in CMOS combinational circuits. | Jiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen |