| 2025 | DAC | Efficient Edge Vision Transformer Accelerator with Decoupled Chunk Attention and Hybrid Computing-In-Memory. | Yi Li, Zijian Ye, Xiangqu Fu, Songqi Wang, Shucheng Du, Ning Lin, Dashan Shang, Jinshan Yue, Zhongrui Wang, Xiaojuan Qi, Feng Zhang, Han Wang |
| 2025 | DAC | An Energy-Efficient High-Utilization Hardware Architecture for Attention Mechanism in Transformer using Balanced Systolic Array and Multi-Row Interleaved Operation Ordering. | Haiyang Zhou, Hongyang Hu, Jinshan Yue, Hanghang Gao, Yuanlu Xie, Xiaoxin Xu, Chunmeng Dou, Ming Liu |
| 2024 | DAC | IG-CRM: Area/Energy-Efficient IGZO-Based Circuits and Architecture Design for Reconfigurable CIM/CAM Applications. | Zeyu Guo, Jinshan Yue, Shengzhe Yan, Zhuoyu Dai, Xiangqu Fu, Zhaori Cong, Zening Niu, Ke Hu, Lihua Xu, Jiawei Wang, Lingfei Wang, Guanhua Yang, Di Geng, Ling Li |
| 2024 | ISCAS | A 2T P-Channel Logic Flash Cell for Reconfigurable Interconnection in Chiplet-Based Computing-In-Memory Accelerators. | Weizeng Li, Linfang Wang, Zhi Li, Wang Ye, Zhidao Zhou, Haiyang Zhou, Hanghang Gao, Jinshan Yue, Hongyang Hu, Fengman Liu, Qing Luo, Chunmeng Dou |
| 2023 | ISCAS | A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture. | Zi Wang, Jinshan Yue, Chaojie He, Zhuoyu Dai, Feibin Xiang, Zhaori Cong, Yifan He, Xiaoyu Feng, Yongpan Liu |
| 2022 | ASPDAC | Sparsity-Aware Non-Volatile Computing-In-Memory Macro with Analog Switch Array and Low-Resolution Current-Mode ADC. | Yuxuan Huang, Yifan He, Jinshan Yue, Wenyu Sun, Huazhong Yang, Yongpan Liu |
| 2022 | ASPDAC | Toward Low-Bit Neural Network Training Accelerator by Dynamic Group Accumulation. | Yixiong Yang, Ruoyang Liu, Wenyu Sun, Jinshan Yue, Huazhong Yang, Yongpan Liu |
| 2022 | ISCAS | C-RRAM: A Fully Input Parallel Charge-Domain RRAM-based Computing-in-Memory Design with High Tolerance for RRAM Variations. | Yifan He, Yuxuan Huang, Jinshan Yue, Wenyu Sun, Lu Zhang, Yongpan Liu |
| 2021 | ASPDAC | Block-Circulant Neural Network Accelerator Featuring Fine-Grained Frequency-Domain Quantization and Reconfigurable FFT Modules. | Yifan He, Jinshan Yue, Yongpan Liu, Huazhong Yang |
| 2021 | ASPDAC | A Non-Volatile Computing-In-Memory Framework With Margin Enhancement Based CSA and Offset Reduction Based ADC. | Yuxuan Huang, Yifan He, Jinshan Yue, Huazhong Yang, Yongpan Liu |
| 2020 | DAC | High PE Utilization CNN Accelerator with Channel Fusion Supporting Pattern-Compressed Sparse Neural Networks. | Jingyu Wang, Songming Yu, Jinshan Yue, Zhe Yuan, Zhuqing Yuan, Huazhong Yang, Xueqing Li, Yongpan Liu |
| 2020 | ISCAS | RL Based Network Accelerator Compiler for Joint Compression Hyper-Parameter Search. | Xiaoyu Feng, Jinshan Yue, Zhe Yuan, Huazhong Yang, Yongpan Liu |
| 2019 | ASPDAC | AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip. | Jinshan Yue, Yongpan Liu, Fang Su, Shuangchen Li, Zhe Yuan, Zhibo Wang, Wenyu Sun, Xueqing Li, Huazhong Yang |
| 2017 | ICCAD | CNN-based pattern recognition on nonvolatile IoT platform for smart ultraviolet monitoring: (Invited paper). | Jinyang Li, Qingwei Guo, Fang Su, Zhe Yuan, Jinshan Yue, Jingtong Hu, Huazhong Yang, Yongpan Liu |
| 2017 | ISLPED | CORAL: Coarse-grained reconfigurable architecture for Convolutional Neural Networks. | Zhe Yuan, Yongpan Liu, Jinshan Yue, Jinyang Li, Huazhong Yang |
| 2016 | DAC | Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead. | Hehe Li, Yongpan Liu, Chenchen Fu, Chun Jason Xue, Donglai Xiang, Jinshan Yue, Jinyang Li, Daming Zhang, Jingtong Hu, Huazhong Yang |