| 2008 | ISCAS | Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4: 2: 2 H.264/AVC encoder LSI. | Takayuki Onishi, Takashi Sano, Koyo Nitta, Mitsuo Ikeda, Jiro Naganuma |
| 2004 | ISCAS | A distributed TS-MUX architecture for multi-chip extension beyond the HDTV level. | Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Makoto Endo, Yoshiyuki Yashima |
| 2003 | DATE | Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level. | Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo |
| 1999 | DATE | An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture. | Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Jiro Naganuma, Takeshi Ogura |
| 1999 | DATE | High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit. | Katsuyuki Ochiai, Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Takeshi Ogura |
| 1999 | RTCSA | On-Chip Multimedia Real-Time OS and its MPEG-2 Applications. | Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Takeshi Ogura |
| 1996 | DATE | A Memory-based Architecture for MPEG2 System Protocol LSIs. | Minoru Inamori, Jiro Naganuma, Haruo Wakabayashi, Makoto Endo |