| 2025 | CGI | Methodology and Results of MIC-OPCC: Multi-Indexed Convolution Model for Octree Point Cloud Compression. | Gerald Baulig, Jiun-In Guo |
| 2025 | DCC | MIC-OPCC: Multi-Indexed Convolution Model for Octree Point Cloud Compression. | Gerald Baulig, Jiun-In Guo |
| 2023 | ISCAS | Multi-Scale Dynamic Fixed-Point Quantization and Training for Deep Neural Networks. | Po-Yuan Chen, Hung-Che Lin, Jiun-In Guo |
| 2019 | ICIP | Recognizing Chinese Texts with 3D Convolutional Neural Network. | Kuan-Chou Chen, Guan-Ting Lin, Che-Tsung Lin, Jiun-In Guo |
| 2019 | ICIP | Using C3D to Detect Rear Overtaking Behavior. | Ching-Kai Tseng, Chien-Chih Liao, Po-Chun Shen, Jiun-In Guo |
| 2019 | MMSP | Summary Embedded Deep Learning Object Detection Model Competition. | Jiun-In Guo, Chia-Chi Tsai, Yong-Hsiang Yang, Hung-Wei Lin, Bo-Xun Wu, Ted T. Kuo, Li-Jen Wang |
| 2018 | ISCAS | A Blind Spot Detection Warning System based on Gabor Filtering and Optical Flow for E-mirror Applications. | Shun-Min Chang, Chia-Chi Tsai, Jiun-In Guo |
| 2016 | ASPDAC | A variable-voltage low-power technique for digital circuit system. | An-Tai Xiao, Yung-Siang Miao, Ching-Hwa Cheng, Jiun-In Guo |
| 2016 | ISCAS | Algorithm derivation and its embedded system realization of speed limit detection for multiple countries. | Yi-Ting Lin, Ting Chou, M. S. Vinay, Jiun-In Guo |
| 2015 | ISCAS | A wireless panoramic endoscope system design and implementation for minimally invasive surgery. | Ching-Hwa Cheng, Sheng-Ping Hung, Jiun-In Guo, Kai-Che Liu, Jungle Chi-Hsiang Wu |
| 2013 | ISCAS | A low-cost scalable Voltage-Frequency Adjustor for implementing low-power systems. | Ching-Hwa Cheng, Sheng-Wei Hsu, Jiun-In Guo |
| 2012 | ISCAS | A two level mode decision algorithm for H.264 high profile intra encoding. | Cheng-Yen Chang, Cheng-An Chien, Hsiu-Cheng Chang, Jia-Wei Chen, Jiun-In Guo |
| 2012 | VCIP | 3D depth map generation for embedded stereo applications. | Jui-Sheng Lee, Guo-An Jian, Cheng-An Chien, Peng-Sheng Chen, Jiun-In Guo |
| 2011 | ASPDAC | A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. | Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng |
| 2011 | ASPDAC | Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism. | Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo |
| 2011 | ASPDAC | A low-power management technique for high-performance domino circuits. | Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo |
| 2010 | ASPDAC | Dynamic voltage domain assignment technique for low power performance manageable cell based design. | Elone Lee, Feng-Tso Chien, Ching-Hwa Cheng, Jiun-In Guo |
| 2010 | ISCAS | A group of macroblock based motion estimation algorithm supporting adaptive search range for H.264 video coding. | Chang-Hung Tsai, Kheng-Joo Tan, Ching-Lung Su, Jiun-In Guo |
| 2009 | ASPDAC | A dynamic quality-scalable H.264 video encoder chip. | Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang |
| 2009 | ASPDAC | CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction. | Chin-Hsien Wang, Ching-Hwa Cheng, Jiun-In Guo |
| 2009 | ISCAS | A Dynamic Quality-scalable H.264 Video Encoder. | Hsiu-Cheng Chang, Jia-Wei Chen, Yao-Chang Yang, Cheng-An Chien, Tzu-Chun Chang, Jinn-Shyan Wang, Jiun-In Guo |
| 2009 | ISCAS | A Multi-standard Video Decoder for High Definition Video Applications. | Cheng-An Chien, Chih-Da Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng |
| 2009 | ISCAS | A High Throughput Deblocking Filter Design Supporting Multiple Video Coding Standards. | Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo |
| 2009 | ISCAS | A System Architecture Exploration on the Configurable HW/SW Co-design for H.264 Video Decoder. | Guo-An Jian, Jui-Chin Chu, Ting-Yu Huang, Tao-Cheng Chang, Jiun-In Guo |
| 2008 | ICASSP | Joint algorithm/code-level optimization of H.264 video decoder for mobile multimedia applications. | Ting-Yu Huang, Guo-An Jian, Jui-Chin Chu, Ching-Lung Su, Jiun-In Guo |
| 2008 | ICASSP | A H.264 basic-unit level rate control algorithm facilitating hardware realization. | Ping-Tsung Wu, Tzu-Chun Chang, Ching-Lung Su, Jiun-In Guo |
| 2007 | DAC | An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model. | Jui-Chin Chu, Wei-Chun Ku, Shu-Hsuan Chou, Tien-Fu Chen, Jiun-In Guo |
| 2007 | ISCAS | A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique. | Kuan-Hung Chen, Yuan-Sun Chu, Yu-Min Chen, Jiun-In Guo |
| 2007 | ISCAS | A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation. | Guo-An Jian, Chih-Da Chien, Jiun-In Guo |
| 2006 | ICASSP | Low Complexity Architecture Design of H.264 Predictive Pixel Compensator for HDTV Application. | Jia-Wei Chen, Chien-Chang Lin, Jiun-In Guo, Jinn-Shyan Wang |
| 2006 | ISCAS | Low-power mechanism with power block management. | Kuo-Chuan Chao, Kuan-Hung Chen, Yuan-Sun Chu, Jiun-In Guo |
| 2006 | ISCAS | A performance-aware IP core design for multimode transform coding using scalable-DA algorithm. | Jia-Wei Chen, Kuan-Hung Chen, Jinn-Shyan Wang, Jiun-In Guo |
| 2006 | ISCAS | A high performance CAVLC encoder design for MPEG-4 AVC/H.264 video coding applications. | Chih-Da Chien, Keng-Po Lu, Yi-Hung Shih, Jiun-In Guo |
| 2006 | ISCAS | Design of customized functional units for the VLIW-based multi-threading processor core targeted at multimedia applications. | Jui-Chin Chu, Chih-Wen Huang, He-Chun Chen, Keng-Po Lu, Ming-Shuan Lee, Jiun-In Guo, Tien-Fu Chen |
| 2005 | ISCAS | A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding. | Hsiu-Cheng Chang, Chien-Chang Lin, Jiun-In Guo |
| 2005 | ISCAS | An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264. | Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang |
| 2005 | ISCAS | A low-power motion compensation IP core design for MPEG-1/2/4 video decoding. | Chih-Da Chien, Ho-Chun Chen, Lin-Chieh Huang, Jiun-In Guo |
| 2005 | ISLPED | An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design. | Kuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Yuan-Sun Chu, Jiun-In Guo |
| 2004 | ISCAS | A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. | Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen |
| 2004 | ISCAS | A power-aware IP core generator for the one-dimensional discrete Fourier transform. | Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo, Tien-Fu Chen |
| 2004 | ISCAS | A parameterized power-aware IP core generator for the 2-D 88 DCT/IDCT. | Rei-Chin Ju, Jia-Wei Chen, Jiun-In Guo, Tien-Fu Chen |
| 2003 | ISCAS | A memory efficient realization of cyclic convolution and its application to discrete cosine transform. | Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen |
| 2003 | ISCAS | A new 2-D 8×8 DCT/IDT core design using group distributed arithmetic. | Jiun-In Guo, Jia-Wei Chen, Han-Chen Chen |
| 2003 | ISCAS | A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining. | Jiun-In Guo, Chih-Da Chien, Chien-Chang Lin |
| 2002 | ISCAS | A new group distributed arithmetic design for the one dimensional discrete Fourier transform. | Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen |
| 2002 | ISCAS | A new hardware efficient design for the one dimensional discrete Fourier transform. | Jiun-In Guo, Chien-Chang Lin |
| 2002 | ISCAS | Design of a new signal security system. | Jui-Cheng Yen, Jiun-In Guo |
| 2001 | ISCAS | A low cost 2-D inverse discrete cosine transform design for image compression. | Jiun-In Guo |
| 2001 | ISCAS | A new DA-based array for one dimensional discrete Hartley transform. | Jiun-In Guo |
| 2000 | ISCAS | An efficient design for one dimensional discrete cosine transform using parallel adders. | Jiun-In Guo |
| 2000 | ISCAS | A new chaotic key-based design for image encryption and decryption. | Jui-Cheng Yen, Jiun-In Guo |
| 1994 | ICASSP | A novel VLSI array design for the discrete Hartley transform using cyclic convolution. | Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen |
| 1994 | ISCAS | A General Approach to Design VLSI Arrays for the Multi-dimensional Discrete Hartley Transform. | Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen |
| 1993 | ISCAS | A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform. | Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen |
| 1993 | ISCAS | A Multi-phase Shared Bus Structure for the Fast Fourier Transform. | Yu-Sheng Lin, Jiun-In Guo, C. Bernard Shung, Chein-Wei Jen |
| 1992 | ICASSP | A memory-based approach to design and implement systolic arrays for DFT and DCT. | Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen |