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Jongsun Park

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

50

Venues

8

Active years

2000–2026

Best venue rank

A*

Where they publish

Papers

50 indexed papers, newest first.

YearVenueTitleAuthors
2026DATEC-STEP: Compute-Efficient Spiking Transformers with Temporal Exit and Early-Guided Pruning.Kyungchul Lee, Jongsun Park
2026DATEHINT: A Hybrid SRAM-MRAM Compute-In-Memory with INput-aware Skipping SAR-ADC for Energy Efficient Ternary LLMs.Jaebeom Park, Seung-Eon Hwang, Jongsun Park
2026ISCASA FeFET-based Approximate DCIM Integrating Multiplication and OR Addition In-Bitcell.Jangseok Yu, Taehwan Kim, Seunghwa Hyun, Jongsun Park
2026ISLPEDFUSE-GS: Frequency-Aware Pruning and Scale-Driven Rendering for Energy Efficient 3D Gaussian Splatting.Hanjun Choi, Hyerin Lim, Joongho Jo, Byeonghun Kwon, Jongsun Park
2026ISLPEDViViD-GS: Voxel-Constrained Representation and Voxel-Centric Accelerator for Real-Time 3D Gaussian Splatting.Seung-Eon Hwang, Jongsun Park
2025DACGS-TG: 3D Gaussian Splatting Accelerator with Tile Grouping for Reducing Redundant Sorting while Preserving Rasterization Efficiency.Joongho Jo, Jongsun Park
2025DACGLOVA: Global and Local Variation-Aware Analog Circuit Design with Risk-Sensitive Reinforcement Learning.Dongjun Kim, Junwoo Park, Chaehyeon Shin, Jaeheon Jung, Kyungho Shin, Seungheon Baek, Sanghyuk Heo, Woongrae Kim, In-Chul Jeong, Joohwan Cho, Jongsun Park
2025DATEPS-GS: Group-Wise Parallel Rendering with Stage-Wise Complexity Reductions for Real-Time 3D Gaussian Splatting.Joongho Jo, Jongsun Park
2025DATESpeeding-Up Successive Read Operations of STT-MRAM via Read Path Alternation for Delay Symmetry.Taehwan Kim, Jongsun Park
2025ICCADSiGNoR: Similarity-based Graph Partitioning and Node Reuse for Memory Efficient GNN Acceleration.Seung-Eon Hwang, Hyeon Gwon Kim, Dongwoo Lew, Jongsun Park
2025ISCASA Pre-charge based Data Cell Dynamic Reference Sensing Scheme for Reliable Read Operations in STT-MRAM.Kyongsoo Kim, Taehwan Kim, Jongsun Park
2024DACSpARC: Token Similarity-Aware Sparse Attention Transformer Accelerator via Row-wise Clustering.Han Cho, Dongjun Kim, Seung-Eon Hwang, Jongsun Park
2024ICCADTP-DCIM: Transposable Digital SRAM CIM Architecture for Energy-Efficient and High Throughput Transformer Acceleration.Junwoo Park, Kyeongho Lee, Jongsun Park
2024ISCASHeNCoG: A Heterogeneous Near-memory Computing Architecture for Energy Efficient GCN Acceleration.Seung-Eon Hwang, Duyeong Song, Jongsun Park
2024ISLPEDSTT-MRAM-based Near-Memory Computing Architecture with Read Scheme and Dataflow Co-Design for High-Throughput and Energy-Efficiency.Yunho Jang, Yeseul Kim, Jongsun Park
2024ISLPEDiSPADE: End-to-end Sparse Architecture for Dense DNN Acceleration via Inverted-bit Representation.Dongjun Kim, Han Cho, Jongsun Park
2022DACA time-to-first-spike coding and conversion aware training for energy-efficient deep spiking neural network processor design.Dongwoo Lew, Kyungchul Lee, Jongsun Park
2022ICCADLow-Cost 7T-SRAM Compute-in-Memory Design Based on Bit-Line Charge-Sharing Based Analog-to-Digital Conversion.Kyeongho Lee, Joonhyung Kim, Jongsun Park
2022ISLPEDA Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing.Joonhyung Kim, Kyeongho Lee, Jongsun Park
2021DACA Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration.Kyeongho Lee, Sungsoo Cheon, Joongho Jo, Woong Choi, Jongsun Park
2021IJCNNAn Energy-Efficient SNN Processor Design based on Sparse Direct Feedback and Spike Prediction.Seunghwan Bang, Dongwoo Lew, Sunghyun Choi, Jongsun Park
2021ISCASLow Cost Heterogeneous ARIA S-Box Implementation for CPA-Resistance.Junghoon Cho, Junhyun Song, Jongsun Park
2021ISCASLow Energy Domain Wall Memory Based Convolution Neural Network Design with Optimizing MAC Architecture.Jooyoon Kim, Yunho Jang, Taehwan Kim, Jongsun Park
2020DACBit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision.Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park
2020DACPrediction Confidence based Low Complexity Gradient Computation for Accelerating DNN Training.Dongyeob Shin, Geonho Kim, Joongho Jo, Jongsun Park
2020ISCASDynamic-Reference Based Early Write Termination for Low Energy SOT-MRAM.Taehwan Kim, Eunjong Yeo, Yunho Jang, Yeongkyo Seo, Jongsun Park
2019DACSensitivity based Error Resilient Techniques for Energy Efficient Deep Neural Network Accelerators.Wonseok Choi, Dongyeob Shin, Jongsun Park, Swaroop Ghosh
2019ISCASLow Cost Ternary Content Addressable Memory Based on Early Termination Precharge Scheme.Kyeongho Lee, Geon Ko, Jongsun Park
2019ISLPEDAn Energy-efficient On-chip Learning Architecture for STDP based Sparse Coding.Heetak Kim, Hoyoung Tang, Jongsun Park
2018DACContent addressable memory based binarized neural network accelerator using time-domain signal processing.Woong Choi, Kwanghyo Jeong, Kyungrak Choi, Kyeongho Lee, Jongsun Park
2018IJCNNSpike Counts Based Low Complexity Learning with Binary Synapse.Hoyoung Tang, Heetak Kim, Donghyeon Cho, Jongsun Park
2018ISCASLow Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme.Woong Choi, Kyeongho Lee, Jongsun Park
2018ISCASCharge-Recycling based Redundant Write Prevention Technique for Low Power SOT-MRAM.Gyuseong Kang, Yunho Jang, Jongsun Park
2018ISLPEDSpin Orbit Torque Device based Stochastic Multi-bit Synapses for On-chip STDP Learning.Gyuseong Kang, Yunho Jang, Jongsun Park
2017ISLPEDBit-width reduction and customized register for low cost convolutional neural network accelerator.Kyungrak Choi, Woong Choi, Kyungho Shin, Jongsun Park
2016ISLPEDDomain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency.Jinil Chung, Jongsun Park, Swaroop Ghosh
2015DACDomain wall memory based digital signal processors for area and energy-efficiency.Jinil Chung, Kenneth Ramclam, Jongsun Park, Swaroop Ghosh
2015DACSelf-correcting STTRAM under magnetic field attacks.Jae-Won Jang, Jongsun Park, Swaroop Ghosh, Swarup Bhunia
2015ISCASA hybrid multimode BCH encoder architecture for area efficient re-encoding approach.Hoyoung Tang, Gihoon Jung, Jongsun Park
2014ISCASA low-complexity composite QR decomposition architecture for MIMO detector.Ji-Hwan Yoon, Dongyeob Shin, Jongsun Park
2013ISCASMultidimensional Householder based high-speed QR decomposition architecture for MIMO receivers.Iput Heri Kurniawan, Ji-Hwan Yoon, Jongsun Park
2012ISCASDual queue based rate selecting schedule for throughput enhancement in WLANs.Dongwan Kim, Wan-Seon Lim, Jongsun Park
2012ISCASHigh-speed tournament givens rotation-based QR Decomposition Architecture for MIMO Receiver.Min-Woo Lee, Ji-Hwan Yoon, Jongsun Park
2011VTCImproved MIMO SIC Detection Exploiting ML Criterion.Ji-Woong Choi, Jungwon Lee, Hui-Ling Lou, Jongsun Park
2006DATEDynamic bit-width adaptation in DCT: image quality versus computation energy trade-off.Jongsun Park, Jung Hwan Choi, Kaushik Roy
2004ICASSPA low power reconfigurable DCT architecture to trade off image quality for computational complexity.Jongsun Park, Kaushik Roy
2004ICASSPHardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering.Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy
2002ICASSPLow power reconfigurable DCT design based on sharing multiplication.Jongsun Park, Soonkeon Kwon, Kaushik Roy
2002ISLPEDHigh performance and low power FIR filter design based on sharing multiplication.Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy
2000ICASSPNon-adaptive and adaptive filter implementation based on sharing multiplication.Jongsun Park, Hunsoo Choo, Khurram Muhammad, Seung Hoon Choi, Yonghee Im, Kaushik Roy