| 2001 | ISCAS | Steiner tree optimization for buffers. Blockages and bays. | Charles J. Alpert, Gopal Gandham, Jiang Hu, Jos Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar |
| 2000 | ICCD | Buffer Library Selection. | Jos Luis Neves, Stephen T. Quay |
| 1999 | DAC | Equivalent Elmore Delay for | Yehea I. Ismail, Eby G. Friedman, Jos Luis Neves |
| 1999 | ICCAD | Repeater insertion in tree structured inductive interconnect. | Yehea I. Ismail, Eby G. Friedman, Jos Luis Neves |
| 1999 | ISCAS | Signal waveform characterization in RLC trees. | Yehea I. Ismail, Eby G. Friedman, Jos Luis Neves |
| 1998 | DAC | Figures of Merit to Characterize the Importance of On-Chip Inductance. | Yehea I. Ismail, Eby G. Friedman, Jos Luis Neves |
| 1998 | ISLPED | Power dissipated by CMOS gates driving lossless transmission lines. | Yehea I. Ismail, Eby G. Friedman, Jos Luis Neves |
| 1996 | DAC | Optimal Clock Skew Scheduling Tolerant to Process Variations. | Jos Luis Neves, Eby G. Friedman |
| 1995 | ISCAS | Minimizing Power Dissipation in Non-Zero Skew-Based Clock Distribution Networks. | Jos Luis Neves, Eby G. Friedman |
| 1994 | ISCAS | Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock Skew. | Jos Luis Neves, Eby G. Friedman |