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Joseph J. Sharkey

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

12

Venues

8

Active years

2005–2008

Best venue rank

A*

Where they publish

Papers

12 indexed papers, newest first.

YearVenueTitleAuthors
2008SBAC-PADHiding Communication Delays in Clustered Microarchitectures.Robert J. LaDuca, Joseph J. Sharkey, Dmitry V. Ponomarev
2007ICSAn L2-miss-driven early register deallocation for SMT processors.Joseph J. Sharkey, Dmitry V. Ponomarev
2007ISLPEDEvaluating design tradeoffs in on-chip power management for CMPs.Joseph J. Sharkey, Alper Buyuktosunoglu, Pradip Bose
2006HiPCTrade-Offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors.Joseph J. Sharkey, Nayef Abu-Ghazeleh, Dmitry V. Ponomarev, Kanad Ghose, Aneesh Aggarwal
2006HPCAEfficient instruction schedulers for SMT processors.Joseph J. Sharkey, Dmitry V. Ponomarev
2006ICPPAddress-Value Decoupling for Early Register Deallocation.Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Aneesh Aggarwal
2006ICPPBalancing ILP and TLP in SMT Architectures through Out-of-Order Instruction Dispatch.Joseph J. Sharkey, Dmitry Ponomarev
2006ISLPEDSelective writeback: exploiting transient values for energy-efficiency and performance.Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose
2005EuroParNon-uniform Instruction Scheduling.Joseph J. Sharkey, Dmitry V. Ponomarev
2005EuroParInstruction Recirculation: Eliminating Counting Logic in Wakeup-Free Schedulers.Joseph J. Sharkey, Dmitry V. Ponomarev
2005ICCDPower-Efficient Wakeup Tag Broadcast.Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomarev, Oguz Ergin
2005ISLPEDInstruction packing: reducing power and delay of the dynamic scheduling logic.Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin