Junghyun Yoon
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
3
Active years
2025–2026
Best venue rank
A*
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ASPDAC | Standard Cell Layout Generation: Methodological Evolution and Architectural Impacts. | Junghyun Yoon, Ikkyum Kim, Gyumin Kim, Sojung Park, Heechun Park |
| 2026 | ASPDAC | SMT-Based Optimal Transistor Folding and Placement for Standard Cell Layout Generation. | Junghyun Yoon, Heechun Park |
| 2026 | DATE | Breaking Standard Cell Margin Constraints for Area-Efficient VLSI Design. | Junghyun Yoon, Jooyeon Jeong, Heechun Park |
| 2025 | DAC | Mitigating Routability Problems in Complementary-FET-based VLSI Designs. | Junghyun Yoon, Heechun Park |