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Juraj Brenkus

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

11

Venues

1

Active years

2008–2019

Best venue rank

C

Where they publish

Papers

11 indexed papers, newest first.

YearVenueTitleAuthors
2019DDECSHigh side power MOSFET switch driver for a low-power AC/DC converter.Miroslav Potocn, Juraj Brenkus, Viera Stopjakov
2016DDECSLow-voltage bulk-driven variable gain amplifier in 130 nm CMOS technology.Daniel Arbet, Martin Kovc, Luks Nagy, Viera Stopjakov, Juraj Brenkus
2016DDECSImpedance calculation based method for AC fault analysis of mixed-signal circuits.Juraj Brenkus, Viera Stopjakov, Luks Nagy, Daniel Arbet
2014DDECSA novel impedance calculation method and its time efficiency evaluation.Juraj Brenkus, Viera Stopjakov, Daniel Arbet, Gbor Gyepes, Libor Majer
2013DDECSNumerical method for DC fault analysis simplification and simulation time reduction.Juraj Brenkus, Viera Stopjakov, Gbor Gyepes
2012DDECSOBIST strategy versus parametric test - Efficiency in covering catastrophic faults in active analog filters.Daniel Arbet, Gbor Gyepes, Juraj Brenkus, Viera Stopjakov
2012DDECSApplication of IDDT test towards increasing SRAM reliability in nanometer technologies.Gbor Gyepes, Daniel Arbet, Juraj Brenkus, Viera Stopjakov
2011DDECSIncreasing the efficiency of analog OBIST using on-chip compensation of technology variations.Daniel Arbet, Juraj Brenkus, Gbor Gyepes, Viera Stopjakov
2011DDECSComparison of iddt test efficiency in covering opens in SRAMs realised in two different technologies.Gbor Gyepes, Juraj Brenkus, Daniel Arbet, Viera Stopjakov
2009DDECSComparison of different test strategies on a mixed-signal circuit.Juraj Brenkus, Viera Stopjakov, Ronny Vanhooren, Anton Chichkov
2008DDECSExperimental Analog Circuit for Parametric Test Methods Efficiency Evaluation.Juraj Brenkus, Viera Stopjakov, Jozef Mihlov