| 2024 | DAC | Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs. | Yuan Pu, Fangzhou Liu, Yu Zhang, Zhuolun He, Yibo Lin, Kai-Yuan Chao, Bei Yu |
| 2023 | ICCAD | Multi-Product Optimization for 3D Heterogeneous Integration with D2W Bonding. | Zhen Zhuang, Kai-Yuan Chao, Bei Yu, Tsung-Yi Ho, Martin D. F. Wong |
| 2022 | ICCAD | Multi-Package Co-Design for Chiplet Integration. | Zhen Zhuang, Bei Yu, Kai-Yuan Chao, Tsung-Yi Ho |
| 2017 | ASPDAC | Delay-driven layer assignment for advanced technology nodes. | Szu-Yuan Han, Wen-Hao Liu, Rickard Ewetz, Cheng-Kok Koh, Kai-Yuan Chao, Ting-Chi Wang |
| 2013 | ASPDAC | Symmetrical buffered clock-tree synthesis with supply-voltage alignment. | Xin-Wei Shih, Tzu-Hsuan Hsu, Hsu-Chieh Lee, Yao-Wen Chang, Kai-Yuan Chao |
| 2012 | ASPDAC | Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded design. | Yuelin Du, Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao |
| 2012 | ICCAD | Scaling the "Memory Wall": Designer track. | Shih-Lien Lu, Tanay Karnik, Ganapati Srinivasa, Kai-Yuan Chao, Doug Carmean, Jim Held |
| 2011 | ASPDAC | Simultaneous redundant via insertion and line end extension for yield optimization. | Shing-Tung Lin, Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao |
| 2011 | ASPDAC | Mask cost reduction with circuit performance consideration for self-aligned double patterning. | Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao |
| 2011 | ICCAD | High-quality global routing for multiple dynamic supply voltage designs. | Wen-Hao Liu, Yih-Lang Li, Kai-Yuan Chao |
| 2010 | ASPDAC | Configurable multi-product floorplanning. | Qiang Ma, Martin D. F. Wong, Kai-Yuan Chao |
| 2010 | ASPDAC | On process-aware 1-D standard cell design. | Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao |
| 2010 | DAC | Multi-threaded collision-aware global routing with bounded-length maze routing. | Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao |
| 2009 | DAC | Spare-cell-aware multilevel analytical placement. | Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yuan Chao |
| 2007 | ASPDAC | Coupling-aware Dummy Metal Insertion for Lithography. | Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang |
| 2006 | ICCAD | Post-routing redundant via insertion and line end extension with via density consideration. | Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao |
| 2003 | ASPDAC | Simultaneous floorplanning and buffer block planning. | Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao |
| 2002 | DATE | Flip-Flop and Repeater Insertion for Early Interconnect Planning. | Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao |
| 2002 | ICCAD | ECO algorithms for removing overlaps between power rails and signal wires. | Hua Xiang, Kai-Yuan Chao, D. F. Wong |
| 1995 | ICCAD | Signal integrity optimization on the pad assignment for high-speed VLSI design. | Kai-Yuan Chao, D. F. Wong |
| 1995 | ICCD | Thermal placement for high-performance multichip modules. | Kai-Yuan Chao, D. F. Wong |
| 1995 | ISCAS | Floorplanning for Low Power Designs. | Kai-Yuan Chao, D. F. Wong |
| 1995 | ISCAS | An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing. | Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong |
| 1994 | ICCAD | Layer assignment for high-performance multi-chip modules. | Kai-Yuan Chao, D. F. Wong |