Kaname Uchikura
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
1
Active years
2004–2006
Best venue rank
National
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2006 | PDPTA | Towards Reconfigurable Cache Memory for a Multithreaded Processor. | Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo |
| 2006 | PDPTA | A Model of Implementable SMT Processor on FPGA. | Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo |
| 2005 | PDPTA | A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. | Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo |
| 2005 | PDPTA | Development of a Thread Scheduler for SMT Processor Architecture. | Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki |
| 2004 | PDPTA | Dynamic Allocation of Physical Register Banks for an SMT Processor. | Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo |