| 2026 | ASPDAC | PigMap3: A Physically Aware Incremental Mapping Framework with On-the-fly Post-Layout Critical Path Tracking. | Hongyang Pan, Cunqing Lan, Zhiang Wang, Xuan Zeng, Fan Yang, Keren Zhu |
| 2026 | DATE | Submodular Maximization-inspired Adaptive Routing Bend Space Planning. | Siting Liu, Peng Xu, Peiyu Liao, Keren Zhu, Yibo Lin, Bei Yu |
| 2026 | FCCM | LENS-HLS: LLM-Enhanced Learning-based Design Space Exploration for High-Level Synthesis. | Yujie Yan, Guanhua Chen, Keren Zhu |
| 2026 | ISCAS | HOLMES: Hierarchical Optimization with poLygonal ModEling for Large-Scale AMS Placement. | Guanhua Chen, Yujie Yan, Jiahua Liu, Zecheng Xu, Linxi Qiu, Yumao Wu, Zhiang Wang, Changhao Yan, Zhaori Bi, Keren Zhu |
| 2026 | ISCAS | PhySeqForm: A Data-Driven, Physical Synthesis Sequence Former. | Cunqing Lan, Zijian Jiang, Hongyang Pan, Zhiang Wang, Keren Zhu |
| 2026 | ISCAS | RC-Scaled Timing-Driven Routing: Bridging Targeted Timing Optimization and Massively. | Parallel Global Routing, Chuyu Wang, Zecheng Xu, Boxiang Song, Zhiang Wang, Fan Yang, Keren Zhu, Xuan Zeng |
| 2026 | ISCAS | Layout-Aware Standard Cell Synthesis via Reparameterization Multi-Task Bayesian Optimization. | Zhouyang Wu, Ruiyu Lyu, Keren Zhu, Zhiang Wang, Zhaori Bi, Changhao Yan, Xuan Zeng |
| 2025 | DAC | MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit Sizing. | Wangzhen Li, Yuan Meng, Ruiyu Lyu, Changhao Yan, Keren Zhu, Zhaori Bi, Dian Zhou, Xuan Zeng |
| 2025 | DAC | Decoupling Analog Circuit Representation from Technology for Behavior-Centric Optimization. | Jintao Li, Haochang Zhi, Jiang Xiao, Keren Zhu, Yun Li |
| 2025 | DATE | ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Synthesis. | Hongyang Pan, Keren Zhu, Fan Yang, Zhufei Chu, Xuan Zeng |
| 2025 | DATE | DAMIL-DCIM: A Digital CIM Layout Synthesis Framework with Dataflow-Aware Floorplan and MILP-Based Detailed Placement. | Chuyu Wang, Ke Hu, Fan Yang, Keren Zhu, Xuan Zeng |
| 2025 | ICCAD | LCTMwalk: GPU-Accelerated Transient Thermal Simulation for Liquid-Cooled 2.5D/3D ICs via Random Walks on Circuit Networks of Modified Compact Thermal Models. | Zhixuan Dong, Yonghan Luo, Yuan Meng, Changhao Yan, Zhaori Bi, Keren Zhu, Sheng-Guo Wang, Dian Zhou, Xuan Zeng |
| 2025 | ICCAD | NSTherm: An Error-Bounded Network-Stochastic Fusion Thermal Simulator for Geometry-Adaptable Chiplets via Diffeomorphic Mapping and Neural-Guided Variance Reduction. | Yuan Meng, Yuyan Wang, Zhixuan Dong, Yonghan Luo, Changhao Yan, Keren Zhu, Zhaori Bi, Sheng-Guo Wang, Dian Zhou, Xuan Zeng |
| 2025 | ICCAD | BAGNet: A Boundary-Aware Graph Neural Network for SRAM Yield Analysis in Post-LayoutSimulation. | Haoyang Sang, Changhao Yan, Zhaori Bi, Keren Zhu, Xuan Zeng |
| 2025 | ICCAD | Seeing Through Designs: Attention-Based Knowledge Transfer for Preference-Guided Microarchitecture Search. | Yiyang Zhao, Xuyang Zhao, Zhaori Bi, Ming Zhu, Qiwei Zhan, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng |
| 2024 | ASPDAC | ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning. | Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Zixuan Jiang, Daniel De Araujo, Douglas Wallace, Douglas Winterberg, Adam R. Klivans, David Z. Pan |
| 2024 | ASPDAC | A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper). | Ruiyu Lyu, Yuan Meng, Aidong Zhao, Zhaori Bi, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng |
| 2024 | ASPDAC | Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper). | Peng Xu, Jintao Li, Tsung-Yi Ho, Bei Yu, Keren Zhu |
| 2024 | DAC | Performance-driven Analog Routing via Heterogeneous 3DGNN and Potential Relaxation. | Peng Xu, Guojin Chen, Keren Zhu, Tinghuan Chen, Tsung-Yi Ho, Bei Yu |
| 2024 | DATE | A Data-Driven Analog Circuit Synthesizer with Automatic Topology Selection and Sizing. | Souradip Poddar, Ahmet Faruk Budak, Linran Zhao, Chen-Hao Hsu, Supriyo Maji, Keren Zhu, Yaoyao Jia, David Z. Pan |
| 2024 | ICCAD | AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis. | Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi, Keren Zhu, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang, Yun Li, Xuan Zeng |
| 2024 | ICCAD | Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis. | Ruiyu Lyu, Aidong Zhao, Yuan Meng, Keren Zhu, Zhaori Bi, Changhao Yan, Fan Yang, Dian Zhou, Xuan Zeng |
| 2024 | ICCAD | Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement. | Hongyang Pan, Cunqing Lan, Yiting Liu, Zhiang Wang, Li Shang, Xuan Zeng, Fan Yang, Keren Zhu |
| 2023 | DATE | ISOP: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design. | Hyunsu Chae, Bhyrav Mutnury, Keren Zhu, Douglas Wallace, Douglas Winterberg, Daniel De Araujo, Jay Reddy, Adam R. Klivans, David Z. Pan |
| 2023 | ICCAD | Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks. | Ahmet Faruk Budak, Keren Zhu, David Z. Pan |
| 2023 | ICCAD | AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search. | Zehua Pei, Fangzhou Liu, Zhuolun He, Guojin Chen, Haisheng Zheng, Keren Zhu, Bei Yu |
| 2022 | ASPDAC | Automating Analog Constraint Extraction: From Heuristics to Learning: (Invited Paper). | Keren Zhu, Hao Chen, Mingjie Liu, David Z. Pan |
| 2022 | ASPDAC | Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits. | Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, David Z. Pan |
| 2022 | ASPDAC | Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives: (Invited Paper). | Ahmet Faruk Budak, Zixuan Jiang, Keren Zhu, Azalia Mirhoseini, Anna Goldie, David Z. Pan |
| 2022 | ICCAD | TAG: Learning Circuit Spatial Embedding from Layouts. | Keren Zhu, Hao Chen, Walker J. Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing Ren |
| 2022 | ICCAD | Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration. | Hanqing Zhu, Keren Zhu, Jiaqi Gu, Harrison Jin, Ray T. Chen, Jean Anne C. Incorvia, David Z. Pan |
| 2021 | DAC | Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks. | Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan |
| 2021 | ICCAD | OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler. | Mingjie Liu, Xiyuan Tang, Keren Zhu, Hao Chen, Nan Sun, David Z. Pan |
| 2020 | ASPDAC | S | Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan |
| 2020 | DAC | Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis. | Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, David Z. Pan |
| 2020 | DATE | Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning. | Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan |
| 2020 | ECCV | An Efficient Training Framework for Reversible Neural Architectures. | Zixuan Jiang, Keren Zhu, Mingjie Liu, Jiaqi Gu, David Z. Pan |
| 2020 | ICCAD | Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow. | Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan |
| 2020 | ICCAD | Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits. | Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan |
| 2019 | ICCAD | MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper. | Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan |
| 2019 | ICCAD | GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance. | Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan |