Kiyeon Lee
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
5
Active years
2007–2012
Best venue rank
B
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2012 | ICCD | Design and evaluation of a four-port data cache for high instruction level parallelism reconfigurable processors. | Kiyeon Lee, Moo-Kyoung Chung, Soojung Ryu, Yeon-Gon Cho, Sangyeun Cho |
| 2011 | MASCOTS | In-N-Out: Reproducing Out-of-Order Superscalar Processor Behavior from Reduced In-Order Traces. | Kiyeon Lee, Sangyeun Cho |
| 2011 | MASCOTS | An Analytical Performance Model for Co-management of Last-Level Cache and Bandwidth Sharing. | Taecheol Oh, Kiyeon Lee, Sangyeun Cho |
| 2009 | ISPASS | Accurately approximating superscalar processor performance from traces. | Kiyeon Lee, Shayne Evans, Sangyeun Cho |
| 2008 | ICPP | TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation. | Sangyeun Cho, Socrates Demetriades, Shayne Evans, Lei Jin, Hyunjin Lee, Kiyeon Lee, Michael Moeng |
| 2007 | RTCSA | Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems. | Sangyeun Cho, Lei Jin, Kiyeon Lee |