Skip to content

Koichi Sasada

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

9

Venues

2

Active years

2003–2006

Best venue rank

National

Where they publish

Papers

9 indexed papers, newest first.

YearVenueTitleAuthors
2006PDPTATowards Reconfigurable Cache Memory for a Multithreaded Processor.Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo
2006PDPTAA Model of Implementable SMT Processor on FPGA.Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo
2005OOPSLAYARV: yet another RubyVM: innovating the ruby interpreter.Koichi Sasada
2005PDPTAA New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation.Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
2005PDPTADevelopment of a Thread Scheduler for SMT Processor Architecture.Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki
2004PDPTADynamic Allocation of Physical Register Banks for an SMT Processor.Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
2003PDPTAPerformance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number.Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki
2003PDPTAImplementation and Evaluation of a Thread Library for Multithreaded Architecture.Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki
2003PDPTAA Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture.Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki