Komaragiri Sai Vishwanath Rohit
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2025–2026
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ISCAS | Triple-Packed Posit MAC: Low-Bitwidth Inference via Tri-Product DSP48E2 Overpacking for CNNs. | Nishith Akula, Sujit Ghantasala, Komaragiri Sai Vishwanath Rohit, Rahul Mukundhan, Madhav Rao |
| 2025 | DSD | VPSA: A Vectored Processing Element configured Systolic Array Architecture Generator. | Kanish R, Komaragiri Sai Vishwanath Rohit, Yash Sengupta, Madhav Rao |