Koutaro Hachiya
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
1997–2020
Best venue rank
B
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2020 | DATE | Testing Through Silicon Vias in Power Distribution Network of 3D-IC with Manufacturing Variability Cancellation. | Koutaro Hachiya, Atsushi Kurokawa |
| 2005 | ASPDAC | On-chip thermal gradient analysis and temperature flattening for SoC design. | Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto |
| 1997 | ASPDAC | Enhancement of parallelism for tearing-based circuit simulation. | Koutaro Hachiya, Toshiyuki Saito, Toshiyuki Nakata, Norio Tanabe |