| 2022 | DATE | Practical Substrate Design Considering Symmetrical and Shielding Routes. | Hao-Yu Chi, Simon Yi-Hung Chen, Hung-Ming Chen, Chien-Nan Liu, Yun-Chih Kuo, Ya-Hsin Chang, Kuan-Hsien Ho |
| 2014 | DAC | A New Asynchronous Pipeline Template for Power and Performance Optimization. | Kuan-Hsien Ho, Yao-Wen Chang |
| 2013 | DAC | Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits. | Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang, Hui-Fang Tsao |
| 2012 | ASPDAC | Clock rescheduling for timing engineering change orders. | Kuan-Hsien Ho, Xin-Wei Shih, Jie-Hong R. Jiang |
| 2010 | ASPDAC | TRECO: dynamic technology remapping for timing engineering change orders. | Kuan-Hsien Ho, Jie-Hong R. Jiang, Yao-Wen Chang |
| 2010 | ICCAD | High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees. | Xin-Wei Shih, Hsu-Chieh Lee, Kuan-Hsien Ho, Yao-Wen Chang |
| 2008 | ICCAD | Routing for chip-package-board co-design considering differential pairs. | Jia-Wei Fang, Kuan-Hsien Ho, Yao-Wen Chang |
| 2007 | ICCAD | Skew aware polarity assignment in clock tree. | Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang |