Kyoung-Rok Cho
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
1
Active years
2012–2019
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | ISCAS | Statistical Modeling of Read Static Noise Margin for 6-Transistor SRAM cell. | Byeong-Jun Bang, Hyun-jeong Kwon, Young Hwan Kim, Kyoung-Rok Cho, Hi-Seok Kim |
| 2018 | ISCAS | Extract LUT Logics from a Downloaded Bitstream Data in FPGA. | Minyoung Jeong, Jaeheum Lee, Eungu Jung, Young Hwan Kim, Kyoung-Rok Cho |
| 2012 | ISCAS | Live demonstration: High fill factor CIS based on single inverter architecture. | Sang-Jin Lee, Omid Kavehei, Kamran Eshraghian, Kyoung-Rok Cho |