| 2026 | ASPDAC | REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Models. | Kyungjun Min, Kyumin Cho, Junhwan Jang, Seokhyeong Kang |
| 2025 | ASPDAC | Leveraging Machine Learning Techniques for Traditional EDA Workflow Enhancement. | Jinoh Cho, Jaekyung Im, Jaeseung Lee, Kyungjun Min, Seonghyeon Park, Jaemin Seo, Jongho Yoon, Seokhyeong Kang |
| 2025 | DATE | Improving LLM-Based Verilog Code Generation with Data Augmentation and RL. | Kyungjun Min, Seonghyeon Park, Hyeonwoo Park, Jinoh Cho, Seokhyeong Kang |
| 2024 | DAC | PPA-Relevant Clustering-Driven Placement for Large-Scale VLSI Designs. | Andrew B. Kahng, Seokhyeong Kang, Sayak Kundu, Kyungjun Min, Seonghyeon Park, Bodhisatta Pramanik |
| 2024 | DATE | CTRL-B: Back-End-Of-Line Configuration Pathfinding Using Cross-Technology Transferable Reinforcement Learning. | Sung-Yun Lee, Kyungjun Min, Seokhyeong Kang |
| 2023 | ICCAD | ClusterNet: Routing Congestion Prediction and Optimization Using Netlist Clustering and Graph Neural Networks. | Kyungjun Min, Seongbin Kwon, Sung-Yun Lee, Dohun Kim, Sunghye Park, Seokhyeong Kang |
| 2022 | ASPDAC | Signal-Integrity-Aware Interposer Bus Routing in 2.5D Heterogeneous Integration. | Sung-Yun Lee, Daeyeon Kim, Kyungjun Min, Seokhyeong Kang |