Lars Friebe
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
5
Active years
2000–2005
Best venue rank
Multiconference
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | ICASSP | A multi-core SoC design for advanced image and video compression. | Andreas Dehnhardt, Mark Bernd Kulaczewski, Lars Friebe, Sren Moch, Peter Pirsch, Hans-Joachim Stolberg, Carsten Reuter |
| 2003 | DATE | HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications. | Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sren Moch, Sebastian Flgel, Xun Mao, Mark Bernd Kulaczewski, Heiko Klumann, Peter Pirsch |
| 2003 | ICIP | HiBRID-SoC: a multi-core architecture for image and video applications. | Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sren Moch, Sebastian Flgel, Mark Bernd Kulaczewski, Peter Pirsch |
| 2003 | IGARSS | A compact and flexible multi-DSP system for real-time SAR applications. | Stefan Langemeyer, Helge Kloos, Christian Simon-Klar, Lars Friebe, Willm Hinrichs, Hanno Lieske, Peter Pirsch |
| 2002 | ICASSP | HiPAR-DSP 16, a scalable highly parallel DSP core for system on a chip video- and image processing applications. | Helge Kloos, Jens Peter Wittenburg, Willm Hinrichs, Hanno Lieske, Lars Friebe, C. Klar, Peter Pirsch |
| 2002 | IGARSS | A multi DSP board for real time SAR processing using the HiPAR-DSP 16. | Christian Simon-Klar, Lars Friebe, Helge Kloos, Hanno Lieske, Willm Hinrichs, Peter Pirsch |
| 2000 | ICCD | A Study of Channeled DRAM Memory Architectures. | Lars Friebe, Yoshikazu Yabe, Masato Motomura |