Laurent Fournier
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
1999–2007
Best venue rank
A*
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2007 | DAC | A Framework for the Validation of Processor Architecture Compliance. | Allon Adir, Sigal Asaf, Laurent Fournier, Itai Jaeger, Ofer Peled |
| 1999 | DAC | Developing an Architecture Validation Suite: Applicaiton to the PowerPC Architecture. | Laurent Fournier, Anatoly Koyfman, Moshe Levinger |
| 1999 | DATE | Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator-Application to the x86 Microprocessors Family. | Laurent Fournier, Yaron Arbetman, Moshe Levinger |