| 2021 | ASPDAC | A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs. | Chirag Sudarshan, Taha Soliman, Cecilia De la Parra, Christian Weis, Leonardo Ecco, Matthias Jung, Norbert Wehn, Andre Guntoro |
| 2017 | ASPDAC | Adaptive load distribution in mixed-critical Networks-on-Chip. | Adam Kostrzewa, Sebastian Tobuschat, Leonardo Ecco, Rolf Ernst |
| 2017 | DATE | Architecting high-speed command schedulers for open-row real-time SDRAM controllers. | Leonardo Ecco, Rolf Ernst |
| 2016 | ASPDAC | Dynamic admission control for real-time networks-on-chips. | Adam Kostrzewa, Selma Saidi, Leonardo Ecco, Rolf Ernst |
| 2016 | ECRTS | Minimizing DRAM Rank Switching Overhead for Improved Timing Bounds and Performance. | Leonardo Ecco, Adam Kostrzewa, Rolf Ernst |
| 2015 | RTSS | Improved DRAM Timing Bounds for Real-Time DRAM Controllers with Read/Write Bundling. | Leonardo Ecco, Rolf Ernst |
| 2015 | RTNS | Flexible TDM-based resource management in on-chip networks. | Adam Kostrzewa, Selma Saidi, Leonardo Ecco, Rolf Ernst |
| 2014 | RTCSA | A mixed critical memory controller using bank privatization and fixed priority scheduling. | Leonardo Ecco, Sebastian Tobuschat, Selma Saidi, Rolf Ernst |