Skip to content

Liang-Che Li

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

1

Venues

1

Active years

2015–2015

Best venue rank

B

Where they publish

Papers

1 indexed papers, newest first.

YearVenueTitleAuthors
2015ASPDACAn efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST.Liang-Che Li, Wen-Hsuan Hsu, Kuen-Jong Lee, Chun-Lung Hsu