| 2024 | ISCAS | Design and Analysis of an Energy-efficient Duo-Core SRAM-based Compute-in-Memory Accelerator. | Lih-Yih Chiou, Hong-Ming Shih, Shun-Hsiu Hsu, Zu-Cheng Sheng, Soon-Jyh Chang |
| 2019 | ISCAS | A Reliable Delay-Based Physical Unclonable Function with Dark-Bit Avoidance. | Lih-Yih Chiou, Chung-Han Wu, Po-Cheng Wei |
| 2019 | ISCAS | A Data-Traffic Aware Dynamic Power Management for General-Purpose Graphics Processing Units. | Lih-Yih Chiou, Chao-Kai Yang, Che-Pin Chang |
| 2018 | ISCAS | Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme. | Chi-Ray Huang, Kuan-Lin Wu, Chung-Han Wu, Lih-Yih Chiou |
| 2017 | ISCAS | A novel clock-pulse-width calibration technique for charge redistribution DACs. | Hugo Cruz, Hong-Yi Huang, Ching-Hsing Luo, Lih-Yih Chiou, Shuenn-Yuh Lee |
| 2017 | ISLPED | Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches. | Tsai-Kan Chien, Lih-Yih Chiou, Yi-Sung Tsou, Shyh-Shyuan Sheu, Pei-Hua Wang, Ming-Jinn Tsai, Chih-I Wu |
| 2016 | ASPDAC | A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. | Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin |
| 2016 | ISCAS | A low store energy and robust ReRAM-based flip-flop for normally off microprocessors. | Tsai-Kan Chien, Lih-Yih Chiou, Yao-Chun Chuang, Shyh-Shyuan Sheu, Heng-Yuan Li, Pei-Hua Wang, Tzu-Kun Ku, Ming-Jinn Tsai, Chih-I Wu |
| 2014 | ISCAS | A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits. | Lih-Yih Chiou, Chi-Ray Huang, Ming-Hung Wu |
| 2012 | ISCAS | Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion. | Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou |
| 2011 | ASPDAC | A fast and effective dynamic trace-based method for analyzing architectural performance. | Yi-Siou Chen, Lih-Yih Chiou, Hsun-Hsiang Chang |
| 2007 | ISCAS | An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop. | Lih-Yih Chiou, Shien-Chun Luo |
| 2006 | ISCAS | Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop. | Yen-Ting Liu, Lih-Yih Chiou, Soon-Jyh Chang |
| 2004 | ICASSP | Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering. | Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy |
| 2003 | DATE | Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications. | Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy |
| 2001 | ICASSP | DSP data path synthesis for low-power applications. | Lih-Yih Chiou, Khurram Muhammad, Kaushik Roy |