| 2021 | ISCAS | A RF-DC Rectifier with Dual Voltage Polarity Self-Biasing for Wireless Sensor Node Application. | Teo Boon Chiat Terence, Venkadasamy Navaneethan, Lim Xian Yang, Nardi Utomo, Ziming Liu, Tan Chong Boon, Seah Yun Da Bryan, Ji-Jon Sit, Liter Siek |
| 2021 | ISCAS | Low Voltage Low Power Output Programmable OCL-LDO with Embedded Voltage Reference. | Nardi Utomo, Boon Chiat Terence Teo, Xian Yang Lim, Venkadasamy Navaneethan, Ziming Liu, Chong Boon Tan, Yun Da Bryan Seah, Ying Hung Yvonne Lam, Liter Siek |
| 2019 | ISCAS | A 0.6 V, 1.74 ps Resolution Capacitively Boosted Time-to-Digital Converter in 180 nm CMOS. | Arjun Ramaswami Palaniappan, Liter Siek |
| 2018 | ISCAS | Novel Edge Comparator with Input Time Hysteresis for Improved Edges Arbitration. | Jian Sen Teh, Liter Siek |
| 2018 | ISCAS | A 14-b, 850fs Fully Synthesizable Stochastic-Based Branching Time-to-Digital Converter in 65nm CMOS. | Jian Sen Teh, Liter Siek, Abdel Martinez Alonso, Anugerah Firdauzi, Akira Matsuzawa |
| 2018 | ISCAS | A Fast Transient Response DC-DC Converter with an Active Compensation Capacitor Module. | Mi Zhou, Zhuochao Sun, Zhekai Xiao, Qiong Wei Low, Liter Siek |
| 2017 | ISCAS | A 0.9-V input PWM DCM boost converter with low output ripples and fast load transient response based on a novel square-root voltage mode (SRVM) control approach. | Hao Luo, Liter Siek |
| 2016 | ISCAS | A close-loop time-mode temperature sensor with inaccuracy of -0.6°C/0.5°C from -40°C to 120°C. | Di Zhu, Jiacheng Wang, Liter Siek |
| 2015 | ISCAS | A switched capacitor deadtime controller for DC-DC buck converter. | Chiang Liang Kok, Xin Li, Liter Siek, Di Zhu, Junjie Kong |
| 2015 | ISCAS | A 9-bit body-biased vernier ring time-to-digital converter in 65 nm CMOS technology. | Junjie Kong, Liter Siek, Chiang Liang Kok |
| 2015 | ISCAS | A higher order curvature corrected 2 ppm/°C CMOS voltage reference circuit. | Arjun Ramaswami Palaniappan, Dominic Maurath, Felix Kalathiparambil, Liter Siek |
| 2015 | ISCAS | A digital time skew calibration technique for time-interleaved ADCs. | Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek |
| 2015 | IECON | Design of WPT coils to minimize AC resistance and capacitor stress applied to SS-topology. | Robin Tanzania, Fook Hoong Choo, Liter Siek |
| 2014 | ISCAS | A statistic based time skew calibration method for time-interleaved ADCs. | Lei Qiu, Yuanjin Zheng, Di Zhu, Liter Siek |
| 2014 | ISCAS | A Fixed-frequency hysteretic controlled buck DC-DC converter with improved load regulation. | Zhuochao Sun, Liter Siek, Ravinder Pal Singh, Minkyu Je |
| 2013 | ISCAS | Analysis and design of high performance frequency-interleaved ADC. | Lei Qiu, Yuanjin Zheng, Liter Siek |
| 2012 | ISCAS | A novel analog-to-residue conversion scheme based on clock overlapping technique. | Qi Huang, Di Zhu, Liter Siek |
| 2009 | ISCAS | A Compact Current Mode Neuron Circuit with Gaussian Taper Learning Capability. | Fei Li, Chip-Hong Chang, Liter Siek |
| 2005 | ISCAS | A 0.18-m 10-GHz CMOS ring oscillator for optical transceivers. | Hai Qi Liu, Wang Ling Goh, Liter Siek |
| 2005 | ISCAS | A new 4.3 ppm/°C voltage reference using standard CMOS process with 1V supply voltage. | Q. X. Zhang, Liter Siek |
| 2000 | ISCAS | A low-offset class-AB CMOS operational amplifier. | Pak K. Chan, Liter Siek, Hwee C. Tay, Jing H. Su |
| 1999 | ISCAS | Bulk compensated CMOS squaring circuits. | Pak Kwong Chan, L. S. Ng, Liter Siek, M. S. Tse, J. Y. Ong, K. S. Lok |