Liuxin Lv
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
2024–2026
Best venue rank
A*
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ISCAS | A Low Noise Bio-potential AFE Achieving 300-mV EDO Tolerance and <20-ms-Settling with VCO-based Full Digital DC Servo Loop. | Shengping Lv, Guanzhe Hu, Liuxin Lv, Peng Zhang, Fei Chen, Wen Jia, Shuqiang Lu, Zhihua Wang, Hanjun Jiang |
| 2024 | DAC | Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. | Xujiang Xiang, Zhiheng Yue, Yuxuan Li, Liuxin Lv, Shaojun Wei, Yang Hu, Shouyi Yin |
| 2024 | ISCAS | A Capacitor-Less LDO Regulator Compensated by Adaptive Zero for Zero-Load Stability Enhancement. | Shengping Lv, Zhijie Chen, Peng Zhang, Peiyuan Wan, Liuxin Lv, Hanjun Jiang |